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Add SPV_INTEL_cache_controls extension support (#376)
Specification: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_cache_controls.asciidoc
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12 files changed

+288
-2
lines changed

12 files changed

+288
-2
lines changed

‎include/spirv/unified1/spirv.bf

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -614,6 +614,8 @@ namespace Spv
614614
MMHostInterfaceMaxBurstINTEL = 6181,
615615
MMHostInterfaceWaitRequestINTEL = 6182,
616616
StableKernelArgumentINTEL = 6183,
617+
CacheControlLoadINTEL = 6442,
618+
CacheControlStoreINTEL = 6443,
617619
}
618620

619621
[AllowDuplicates, CRepr] public enum BuiltIn
@@ -1198,6 +1200,7 @@ namespace Spv
11981200
FPGALatencyControlINTEL = 6171,
11991201
FPGAArgumentInterfacesINTEL = 6174,
12001202
GroupUniformArithmeticKHR = 6400,
1203+
CacheControlsINTEL = 6441,
12011204
}
12021205

12031206
[AllowDuplicates, CRepr] public enum RayFlagsShift
@@ -1351,6 +1354,23 @@ namespace Spv
13511354
ReadWriteINTEL = 3,
13521355
}
13531356

1357+
[AllowDuplicates, CRepr] public enum LoadCacheControl
1358+
{
1359+
UncachedINTEL = 0,
1360+
CachedINTEL = 1,
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StreamingINTEL = 2,
1362+
InvalidateAfterReadINTEL = 3,
1363+
ConstCachedINTEL = 4,
1364+
}
1365+
1366+
[AllowDuplicates, CRepr] public enum StoreCacheControl
1367+
{
1368+
UncachedINTEL = 0,
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WriteThroughINTEL = 1,
1370+
WriteBackINTEL = 2,
1371+
StreamingINTEL = 3,
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}
1373+
13541374
[AllowDuplicates, CRepr] public enum Op
13551375
{
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OpNop = 0,

‎include/spirv/unified1/spirv.core.grammar.json

Lines changed: 92 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13642,6 +13642,26 @@
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"value" : 6183,
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"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
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"version" : "None"
13645+
},
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{
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"enumerant" : "CacheControlLoadINTEL",
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"value" : 6442,
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"capabilities" : [ "CacheControlsINTEL" ],
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"parameters" : [
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{ "kind" : "LiteralInteger", "name" : "'Cache Level'" },
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{ "kind" : "LoadCacheControl", "name" : "'Cache Control'" }
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],
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"version" : "None"
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},
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{
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"enumerant" : "CacheControlStoreINTEL",
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"value" : 6443,
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"capabilities" : [ "CacheControlsINTEL" ],
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"parameters" : [
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{ "kind" : "LiteralInteger", "name" : "'Cache Level'" },
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{ "kind" : "StoreCacheControl", "name" : "'Cache Control'" }
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],
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"version" : "None"
1364513665
}
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]
1364713667
},
@@ -16190,6 +16210,12 @@
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"value" : 6400,
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"extensions" : [ "SPV_KHR_uniform_group_instructions"],
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"version" : "None"
16213+
},
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{
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"enumerant" : "CacheControlsINTEL",
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"value" : 6441,
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"extensions" : [ "SPV_INTEL_cache_controls" ],
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"version" : "None"
1619316219
}
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]
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},
@@ -16361,6 +16387,72 @@
1636116387
}
1636216388
]
1636316389
},
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{
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"category" : "ValueEnum",
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"kind" : "LoadCacheControl",
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"enumerants" : [
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{
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"enumerant" : "UncachedINTEL",
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"value" : 0,
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"capabilities" : [ "CacheControlsINTEL" ],
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"version" : "None"
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},
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{
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"enumerant" : "CachedINTEL",
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"value" : 1,
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"capabilities" : [ "CacheControlsINTEL" ],
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"version" : "None"
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},
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{
16407+
"enumerant" : "StreamingINTEL",
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"value" : 2,
16409+
"capabilities" : [ "CacheControlsINTEL" ],
16410+
"version" : "None"
16411+
},
16412+
{
16413+
"enumerant" : "InvalidateAfterReadINTEL",
16414+
"value" : 3,
16415+
"capabilities" : [ "CacheControlsINTEL" ],
16416+
"version" : "None"
16417+
},
16418+
{
16419+
"enumerant" : "ConstCachedINTEL",
16420+
"value" : 4,
16421+
"capabilities" : [ "CacheControlsINTEL" ],
16422+
"version" : "None"
16423+
}
16424+
]
16425+
},
16426+
{
16427+
"category" : "ValueEnum",
16428+
"kind" : "StoreCacheControl",
16429+
"enumerants" : [
16430+
{
16431+
"enumerant" : "UncachedINTEL",
16432+
"value" : 0,
16433+
"capabilities" : [ "CacheControlsINTEL" ],
16434+
"version" : "None"
16435+
},
16436+
{
16437+
"enumerant" : "WriteThroughINTEL",
16438+
"value" : 1,
16439+
"capabilities" : [ "CacheControlsINTEL" ],
16440+
"version" : "None"
16441+
},
16442+
{
16443+
"enumerant" : "WriteBackINTEL",
16444+
"value" : 2,
16445+
"capabilities" : [ "CacheControlsINTEL" ],
16446+
"version" : "None"
16447+
},
16448+
{
16449+
"enumerant" : "StreamingINTEL",
16450+
"value" : 3,
16451+
"capabilities" : [ "CacheControlsINTEL" ],
16452+
"version" : "None"
16453+
}
16454+
]
16455+
},
1636416456
{
1636516457
"category" : "Id",
1636616458
"kind" : "IdResultType",

‎include/spirv/unified1/spirv.cs

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -613,6 +613,8 @@ public enum Decoration
613613
MMHostInterfaceMaxBurstINTEL = 6181,
614614
MMHostInterfaceWaitRequestINTEL = 6182,
615615
StableKernelArgumentINTEL = 6183,
616+
CacheControlLoadINTEL = 6442,
617+
CacheControlStoreINTEL = 6443,
616618
}
617619

618620
public enum BuiltIn
@@ -1197,6 +1199,7 @@ public enum Capability
11971199
FPGALatencyControlINTEL = 6171,
11981200
FPGAArgumentInterfacesINTEL = 6174,
11991201
GroupUniformArithmeticKHR = 6400,
1202+
CacheControlsINTEL = 6441,
12001203
}
12011204

12021205
public enum RayFlagsShift
@@ -1350,6 +1353,23 @@ public enum HostAccessQualifier
13501353
ReadWriteINTEL = 3,
13511354
}
13521355

1356+
public enum LoadCacheControl
1357+
{
1358+
UncachedINTEL = 0,
1359+
CachedINTEL = 1,
1360+
StreamingINTEL = 2,
1361+
InvalidateAfterReadINTEL = 3,
1362+
ConstCachedINTEL = 4,
1363+
}
1364+
1365+
public enum StoreCacheControl
1366+
{
1367+
UncachedINTEL = 0,
1368+
WriteThroughINTEL = 1,
1369+
WriteBackINTEL = 2,
1370+
StreamingINTEL = 3,
1371+
}
1372+
13531373
public enum Op
13541374
{
13551375
OpNop = 0,

‎include/spirv/unified1/spirv.h

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -619,6 +619,8 @@ typedef enum SpvDecoration_ {
619619
SpvDecorationMMHostInterfaceMaxBurstINTEL = 6181,
620620
SpvDecorationMMHostInterfaceWaitRequestINTEL = 6182,
621621
SpvDecorationStableKernelArgumentINTEL = 6183,
622+
SpvDecorationCacheControlLoadINTEL = 6442,
623+
SpvDecorationCacheControlStoreINTEL = 6443,
622624
SpvDecorationMax = 0x7fffffff,
623625
} SpvDecoration;
624626

@@ -1197,6 +1199,7 @@ typedef enum SpvCapability_ {
11971199
SpvCapabilityFPGALatencyControlINTEL = 6171,
11981200
SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
11991201
SpvCapabilityGroupUniformArithmeticKHR = 6400,
1202+
SpvCapabilityCacheControlsINTEL = 6441,
12001203
SpvCapabilityMax = 0x7fffffff,
12011204
} SpvCapability;
12021205

@@ -1348,6 +1351,23 @@ typedef enum SpvHostAccessQualifier_ {
13481351
SpvHostAccessQualifierMax = 0x7fffffff,
13491352
} SpvHostAccessQualifier;
13501353

1354+
typedef enum SpvLoadCacheControl_ {
1355+
SpvLoadCacheControlUncachedINTEL = 0,
1356+
SpvLoadCacheControlCachedINTEL = 1,
1357+
SpvLoadCacheControlStreamingINTEL = 2,
1358+
SpvLoadCacheControlInvalidateAfterReadINTEL = 3,
1359+
SpvLoadCacheControlConstCachedINTEL = 4,
1360+
SpvLoadCacheControlMax = 0x7fffffff,
1361+
} SpvLoadCacheControl;
1362+
1363+
typedef enum SpvStoreCacheControl_ {
1364+
SpvStoreCacheControlUncachedINTEL = 0,
1365+
SpvStoreCacheControlWriteThroughINTEL = 1,
1366+
SpvStoreCacheControlWriteBackINTEL = 2,
1367+
SpvStoreCacheControlStreamingINTEL = 3,
1368+
SpvStoreCacheControlMax = 0x7fffffff,
1369+
} SpvStoreCacheControl;
1370+
13511371
typedef enum SpvOp_ {
13521372
SpvOpNop = 0,
13531373
SpvOpUndef = 1,

‎include/spirv/unified1/spirv.hpp

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Original file line numberDiff line numberDiff line change
@@ -615,6 +615,8 @@ enum Decoration {
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DecorationMMHostInterfaceMaxBurstINTEL = 6181,
616616
DecorationMMHostInterfaceWaitRequestINTEL = 6182,
617617
DecorationStableKernelArgumentINTEL = 6183,
618+
DecorationCacheControlLoadINTEL = 6442,
619+
DecorationCacheControlStoreINTEL = 6443,
618620
DecorationMax = 0x7fffffff,
619621
};
620622

@@ -1193,6 +1195,7 @@ enum Capability {
11931195
CapabilityFPGALatencyControlINTEL = 6171,
11941196
CapabilityFPGAArgumentInterfacesINTEL = 6174,
11951197
CapabilityGroupUniformArithmeticKHR = 6400,
1198+
CapabilityCacheControlsINTEL = 6441,
11961199
CapabilityMax = 0x7fffffff,
11971200
};
11981201

@@ -1344,6 +1347,23 @@ enum HostAccessQualifier {
13441347
HostAccessQualifierMax = 0x7fffffff,
13451348
};
13461349

1350+
enum LoadCacheControl {
1351+
LoadCacheControlUncachedINTEL = 0,
1352+
LoadCacheControlCachedINTEL = 1,
1353+
LoadCacheControlStreamingINTEL = 2,
1354+
LoadCacheControlInvalidateAfterReadINTEL = 3,
1355+
LoadCacheControlConstCachedINTEL = 4,
1356+
LoadCacheControlMax = 0x7fffffff,
1357+
};
1358+
1359+
enum StoreCacheControl {
1360+
StoreCacheControlUncachedINTEL = 0,
1361+
StoreCacheControlWriteThroughINTEL = 1,
1362+
StoreCacheControlWriteBackINTEL = 2,
1363+
StoreCacheControlStreamingINTEL = 3,
1364+
StoreCacheControlMax = 0x7fffffff,
1365+
};
1366+
13471367
enum Op {
13481368
OpNop = 0,
13491369
OpUndef = 1,

‎include/spirv/unified1/spirv.hpp11

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -615,6 +615,8 @@ enum class Decoration : unsigned {
615615
MMHostInterfaceMaxBurstINTEL = 6181,
616616
MMHostInterfaceWaitRequestINTEL = 6182,
617617
StableKernelArgumentINTEL = 6183,
618+
CacheControlLoadINTEL = 6442,
619+
CacheControlStoreINTEL = 6443,
618620
Max = 0x7fffffff,
619621
};
620622

@@ -1193,6 +1195,7 @@ enum class Capability : unsigned {
11931195
FPGALatencyControlINTEL = 6171,
11941196
FPGAArgumentInterfacesINTEL = 6174,
11951197
GroupUniformArithmeticKHR = 6400,
1198+
CacheControlsINTEL = 6441,
11961199
Max = 0x7fffffff,
11971200
};
11981201

@@ -1344,6 +1347,23 @@ enum class HostAccessQualifier : unsigned {
13441347
Max = 0x7fffffff,
13451348
};
13461349

1350+
enum class LoadCacheControl : unsigned {
1351+
UncachedINTEL = 0,
1352+
CachedINTEL = 1,
1353+
StreamingINTEL = 2,
1354+
InvalidateAfterReadINTEL = 3,
1355+
ConstCachedINTEL = 4,
1356+
Max = 0x7fffffff,
1357+
};
1358+
1359+
enum class StoreCacheControl : unsigned {
1360+
UncachedINTEL = 0,
1361+
WriteThroughINTEL = 1,
1362+
WriteBackINTEL = 2,
1363+
StreamingINTEL = 3,
1364+
Max = 0x7fffffff,
1365+
};
1366+
13471367
enum class Op : unsigned {
13481368
OpNop = 0,
13491369
OpUndef = 1,

‎include/spirv/unified1/spirv.json

Lines changed: 28 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -640,7 +640,9 @@
640640
"MMHostInterfaceReadWriteModeINTEL": 6180,
641641
"MMHostInterfaceMaxBurstINTEL": 6181,
642642
"MMHostInterfaceWaitRequestINTEL": 6182,
643-
"StableKernelArgumentINTEL": 6183
643+
"StableKernelArgumentINTEL": 6183,
644+
"CacheControlLoadINTEL": 6442,
645+
"CacheControlStoreINTEL": 6443
644646
}
645647
},
646648
{
@@ -1172,7 +1174,8 @@
11721174
"FPMaxErrorINTEL": 6169,
11731175
"FPGALatencyControlINTEL": 6171,
11741176
"FPGAArgumentInterfacesINTEL": 6174,
1175-
"GroupUniformArithmeticKHR": 6400
1177+
"GroupUniformArithmeticKHR": 6400,
1178+
"CacheControlsINTEL": 6441
11761179
}
11771180
},
11781181
{
@@ -1336,6 +1339,29 @@
13361339
"ReadWriteINTEL": 3
13371340
}
13381341
},
1342+
{
1343+
"Name": "LoadCacheControl",
1344+
"Type": "Value",
1345+
"Values":
1346+
{
1347+
"UncachedINTEL": 0,
1348+
"CachedINTEL": 1,
1349+
"StreamingINTEL": 2,
1350+
"InvalidateAfterReadINTEL": 3,
1351+
"ConstCachedINTEL": 4
1352+
}
1353+
},
1354+
{
1355+
"Name": "StoreCacheControl",
1356+
"Type": "Value",
1357+
"Values":
1358+
{
1359+
"UncachedINTEL": 0,
1360+
"WriteThroughINTEL": 1,
1361+
"WriteBackINTEL": 2,
1362+
"StreamingINTEL": 3
1363+
}
1364+
},
13391365
{
13401366
"Name": "Op",
13411367
"Type": "Value",

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