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miaoqing-pankvalo
miaoqing-pan
authored and
kvalo
committed
ath9k: define correct GPIO numbers and bits mask
Define correct GPIO numbers and MASK bits to indicate the WMAC GPIO resource. Allow SOC chips(AR9340, AR9531, AR9550, AR9561) to access all GPIOs which rely on gpiolib framework. But restrict SOC AR9330 only to access WMAC GPIO which has the same design with the old chips. Signed-off-by: Miaoqing Pan <[email protected]> Signed-off-by: Kalle Valo <[email protected]>
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‎drivers/net/wireless/ath/ath9k/hw.c

Lines changed: 56 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -2385,6 +2385,61 @@ static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
23852385
}
23862386
}
23872387

2388+
static void ath9k_gpio_cap_init(struct ath_hw *ah)
2389+
{
2390+
struct ath9k_hw_capabilities *pCap = &ah->caps;
2391+
2392+
if (AR_SREV_9271(ah)) {
2393+
pCap->num_gpio_pins = AR9271_NUM_GPIO;
2394+
pCap->gpio_mask = AR9271_GPIO_MASK;
2395+
} else if (AR_DEVID_7010(ah)) {
2396+
pCap->num_gpio_pins = AR7010_NUM_GPIO;
2397+
pCap->gpio_mask = AR7010_GPIO_MASK;
2398+
} else if (AR_SREV_9287(ah)) {
2399+
pCap->num_gpio_pins = AR9287_NUM_GPIO;
2400+
pCap->gpio_mask = AR9287_GPIO_MASK;
2401+
} else if (AR_SREV_9285(ah)) {
2402+
pCap->num_gpio_pins = AR9285_NUM_GPIO;
2403+
pCap->gpio_mask = AR9285_GPIO_MASK;
2404+
} else if (AR_SREV_9280(ah)) {
2405+
pCap->num_gpio_pins = AR9280_NUM_GPIO;
2406+
pCap->gpio_mask = AR9280_GPIO_MASK;
2407+
} else if (AR_SREV_9300(ah)) {
2408+
pCap->num_gpio_pins = AR9300_NUM_GPIO;
2409+
pCap->gpio_mask = AR9300_GPIO_MASK;
2410+
} else if (AR_SREV_9330(ah)) {
2411+
pCap->num_gpio_pins = AR9330_NUM_GPIO;
2412+
pCap->gpio_mask = AR9330_GPIO_MASK;
2413+
} else if (AR_SREV_9340(ah)) {
2414+
pCap->num_gpio_pins = AR9340_NUM_GPIO;
2415+
pCap->gpio_mask = AR9340_GPIO_MASK;
2416+
} else if (AR_SREV_9462(ah)) {
2417+
pCap->num_gpio_pins = AR9462_NUM_GPIO;
2418+
pCap->gpio_mask = AR9462_GPIO_MASK;
2419+
} else if (AR_SREV_9485(ah)) {
2420+
pCap->num_gpio_pins = AR9485_NUM_GPIO;
2421+
pCap->gpio_mask = AR9485_GPIO_MASK;
2422+
} else if (AR_SREV_9531(ah)) {
2423+
pCap->num_gpio_pins = AR9531_NUM_GPIO;
2424+
pCap->gpio_mask = AR9531_GPIO_MASK;
2425+
} else if (AR_SREV_9550(ah)) {
2426+
pCap->num_gpio_pins = AR9550_NUM_GPIO;
2427+
pCap->gpio_mask = AR9550_GPIO_MASK;
2428+
} else if (AR_SREV_9561(ah)) {
2429+
pCap->num_gpio_pins = AR9561_NUM_GPIO;
2430+
pCap->gpio_mask = AR9561_GPIO_MASK;
2431+
} else if (AR_SREV_9565(ah)) {
2432+
pCap->num_gpio_pins = AR9565_NUM_GPIO;
2433+
pCap->gpio_mask = AR9565_GPIO_MASK;
2434+
} else if (AR_SREV_9580(ah)) {
2435+
pCap->num_gpio_pins = AR9580_NUM_GPIO;
2436+
pCap->gpio_mask = AR9580_GPIO_MASK;
2437+
} else {
2438+
pCap->num_gpio_pins = AR_NUM_GPIO;
2439+
pCap->gpio_mask = AR_GPIO_MASK;
2440+
}
2441+
}
2442+
23882443
int ath9k_hw_fill_cap_info(struct ath_hw *ah)
23892444
{
23902445
struct ath9k_hw_capabilities *pCap = &ah->caps;
@@ -2478,20 +2533,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
24782533
else
24792534
pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
24802535

2481-
if (AR_SREV_9271(ah))
2482-
pCap->num_gpio_pins = AR9271_NUM_GPIO;
2483-
else if (AR_DEVID_7010(ah))
2484-
pCap->num_gpio_pins = AR7010_NUM_GPIO;
2485-
else if (AR_SREV_9300_20_OR_LATER(ah))
2486-
pCap->num_gpio_pins = AR9300_NUM_GPIO;
2487-
else if (AR_SREV_9287_11_OR_LATER(ah))
2488-
pCap->num_gpio_pins = AR9287_NUM_GPIO;
2489-
else if (AR_SREV_9285_12_OR_LATER(ah))
2490-
pCap->num_gpio_pins = AR9285_NUM_GPIO;
2491-
else if (AR_SREV_9280_20_OR_LATER(ah))
2492-
pCap->num_gpio_pins = AR928X_NUM_GPIO;
2493-
else
2494-
pCap->num_gpio_pins = AR_NUM_GPIO;
2536+
ath9k_gpio_cap_init(ah);
24952537

24962538
if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
24972539
pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;

‎drivers/net/wireless/ath/ath9k/hw.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -301,6 +301,7 @@ struct ath9k_hw_capabilities {
301301
u8 max_txchains;
302302
u8 max_rxchains;
303303
u8 num_gpio_pins;
304+
u32 gpio_mask;
304305
u8 rx_hp_qdepth;
305306
u8 rx_lp_qdepth;
306307
u8 rx_status_len;

‎drivers/net/wireless/ath/ath9k/reg.h

Lines changed: 39 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -985,6 +985,10 @@
985985
#define AR_SREV_9561(_ah) \
986986
(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9561))
987987

988+
#define AR_SREV_SOC(_ah) \
989+
(AR_SREV_9340(_ah) || AR_SREV_9531(_ah) || AR_SREV_9550(ah) || \
990+
AR_SREV_9561(ah))
991+
988992
/* NOTE: When adding chips newer than Peacock, add chip check here */
989993
#define AR_SREV_9580_10_OR_LATER(_ah) \
990994
(AR_SREV_9580(_ah))
@@ -1104,14 +1108,46 @@ enum {
11041108

11051109
#define AR_PCIE_PHY_REG3 0x18c08
11061110

1111+
/* Define correct GPIO numbers and MASK bits to indicate the WMAC
1112+
* GPIO resource.
1113+
* Allow SOC chips(AR9340, AR9531, AR9550, AR9561) to access all GPIOs
1114+
* which rely on gpiolib framework. But restrict SOC AR9330 only to
1115+
* access WMAC GPIO which has the same design with the old chips.
1116+
*/
11071117
#define AR_NUM_GPIO 14
1108-
#define AR928X_NUM_GPIO 10
1118+
#define AR9280_NUM_GPIO 10
11091119
#define AR9285_NUM_GPIO 12
1110-
#define AR9287_NUM_GPIO 11
1120+
#define AR9287_NUM_GPIO 10
11111121
#define AR9271_NUM_GPIO 16
1112-
#define AR9300_NUM_GPIO 17
1122+
#define AR9300_NUM_GPIO 16
1123+
#define AR9330_NUM_GPIO 16
1124+
#define AR9340_NUM_GPIO 23
1125+
#define AR9462_NUM_GPIO 10
1126+
#define AR9485_NUM_GPIO 12
1127+
#define AR9531_NUM_GPIO 18
1128+
#define AR9550_NUM_GPIO 24
1129+
#define AR9561_NUM_GPIO 23
1130+
#define AR9565_NUM_GPIO 12
1131+
#define AR9580_NUM_GPIO 16
11131132
#define AR7010_NUM_GPIO 16
11141133

1134+
#define AR_GPIO_MASK 0x00003FFF
1135+
#define AR9271_GPIO_MASK 0x0000FFFF
1136+
#define AR9280_GPIO_MASK 0x000003FF
1137+
#define AR9285_GPIO_MASK 0x00000FFF
1138+
#define AR9287_GPIO_MASK 0x000003FF
1139+
#define AR9300_GPIO_MASK 0x0000F4FF
1140+
#define AR9330_GPIO_MASK 0x0000F4FF
1141+
#define AR9340_GPIO_MASK 0x0000000F
1142+
#define AR9462_GPIO_MASK 0x000003FF
1143+
#define AR9485_GPIO_MASK 0x00000FFF
1144+
#define AR9531_GPIO_MASK 0x0000000F
1145+
#define AR9550_GPIO_MASK 0x0000000F
1146+
#define AR9561_GPIO_MASK 0x0000000F
1147+
#define AR9565_GPIO_MASK 0x00000FFF
1148+
#define AR9580_GPIO_MASK 0x0000F4FF
1149+
#define AR7010_GPIO_MASK 0x0000FFFF
1150+
11151151
#define AR_GPIO_IN_OUT (AR_SREV_9340(ah) ? 0x4028 : 0x4048)
11161152
#define AR_GPIO_IN_VAL 0x0FFFC000
11171153
#define AR_GPIO_IN_VAL_S 14

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