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Winch: implement rmw xchg for x64 (bytecodealliance#10029)
* implement x64 xchg * fix test post rebase
1 parent 1d1c06f commit 146aa47

12 files changed

+338
-13
lines changed

‎tests/disas/winch/x64/atomic/rmw/i32_atomic_rmw16_xchgu.wat

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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i32)
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(i32.atomic.rmw16.xchg_u (i32.const 0) (i32.const 42))))
8+
;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x10, %r11
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;; cmpq %rsp, %r11
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;; ja 0x5f
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;; 1c: movq %rdi, %r14
17+
;; subq $0x10, %rsp
18+
;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
20+
;; movl $0x2a, %eax
21+
;; movl $0, %ecx
22+
;; andw $1, %cx
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;; cmpw $0, %cx
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;; jne 0x61
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;; 44: movl $0, %ecx
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;; movq 0x58(%r14), %r11
27+
;; movq (%r11), %rdx
28+
;; addq %rcx, %rdx
29+
;; xchgw %ax, (%rdx)
30+
;; movzwl %ax, %eax
31+
;; addq $0x10, %rsp
32+
;; popq %rbp
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;; retq
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;; 5f: ud2
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;; 61: ud2

‎tests/disas/winch/x64/atomic/rmw/i32_atomic_rmw8_xchgu.wat

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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i32)
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(i32.atomic.rmw8.xchg_u (i32.const 0) (i32.const 42))))
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;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x10, %r11
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;; cmpq %rsp, %r11
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;; ja 0x4b
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movl $0x2a, %eax
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;; movl $0, %ecx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rdx
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;; addq %rcx, %rdx
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;; xchgb %al, (%rdx)
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;; movzbl %al, %eax
27+
;; addq $0x10, %rsp
28+
;; popq %rbp
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;; retq
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;; 4b: ud2

‎tests/disas/winch/x64/atomic/rmw/i32_atomic_rmw_xchg.wat

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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i32)
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(i32.atomic.rmw.xchg (i32.const 0) (i32.const 42))))
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;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x10, %r11
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;; cmpq %rsp, %r11
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;; ja 0x59
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movl $0x2a, %eax
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;; movl $0, %ecx
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;; andl $3, %ecx
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;; cmpl $0, %ecx
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;; jne 0x5b
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;; 42: movl $0, %ecx
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;; movq 0x58(%r14), %r11
27+
;; movq (%r11), %rdx
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;; addq %rcx, %rdx
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;; xchgl %eax, (%rdx)
30+
;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 59: ud2
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;; 5b: ud2

‎tests/disas/winch/x64/atomic/rmw/i64_atomic_rmw16_xchgu.wat

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@@ -0,0 +1,35 @@
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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i64)
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(i64.atomic.rmw16.xchg_u (i32.const 0) (i64.const 42))))
8+
;; wasm[0]::function[0]:
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;; pushq %rbp
10+
;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x10, %r11
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;; cmpq %rsp, %r11
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;; ja 0x62
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
20+
;; movq $0x2a, %rax
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;; movl $0, %ecx
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;; andw $1, %cx
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;; cmpw $0, %cx
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;; jne 0x64
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;; 46: movl $0, %ecx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rdx
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;; addq %rcx, %rdx
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;; xchgw %ax, (%rdx)
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;; movzwq %ax, %rax
31+
;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 62: ud2
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;; 64: ud2

‎tests/disas/winch/x64/atomic/rmw/i64_atomic_rmw32_addu.wat

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,27 +4,31 @@
44
(module
55
(memory 1 1 shared)
66
(func (export "_start") (result i64)
7-
(i64.atomic.rmw8.add_u (i32.const 0) (i64.const 42))))
7+
(i64.atomic.rmw32.add_u (i32.const 0) (i64.const 42))))
88
;; wasm[0]::function[0]:
99
;; pushq %rbp
1010
;; movq %rsp, %rbp
1111
;; movq 8(%rdi), %r11
1212
;; movq 0x10(%r11), %r11
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;; addq $0x10, %r11
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;; cmpq %rsp, %r11
15-
;; ja 0x50
15+
;; ja 0x5d
1616
;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
2020
;; movq $0x2a, %rax
2121
;; movl $0, %ecx
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;; andl $3, %ecx
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;; cmpl $0, %ecx
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;; jne 0x5f
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;; 44: movl $0, %ecx
2226
;; movq 0x58(%r14), %r11
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;; movq (%r11), %rdx
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;; addq %rcx, %rdx
25-
;; lock xaddb %al, (%rdx)
26-
;; movzbq %al, %rax
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;; lock xaddl %eax, (%rdx)
2730
;; addq $0x10, %rsp
2831
;; popq %rbp
2932
;; retq
30-
;; 50: ud2
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;; 5d: ud2
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;; 5f: ud2

‎tests/disas/winch/x64/atomic/rmw/i64_atomic_rmw32_xchgu.wat

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@@ -0,0 +1,34 @@
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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i64)
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(i64.atomic.rmw32.xchg_u (i32.const 0) (i64.const 42))))
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;; wasm[0]::function[0]:
9+
;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x10, %r11
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;; cmpq %rsp, %r11
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;; ja 0x5b
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movq $0x2a, %rax
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;; movl $0, %ecx
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;; andl $3, %ecx
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;; cmpl $0, %ecx
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;; jne 0x5d
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;; 44: movl $0, %ecx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rdx
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;; addq %rcx, %rdx
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;; xchgl %eax, (%rdx)
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;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 5b: ud2
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;; 5d: ud2

‎tests/disas/winch/x64/atomic/rmw/i64_atomic_rmw8_xchgu.wat

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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i64)
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(i64.atomic.rmw8.xchg_u (i32.const 0) (i64.const 42))))
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;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x10, %r11
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;; cmpq %rsp, %r11
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;; ja 0x4e
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movq $0x2a, %rax
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;; movl $0, %ecx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rdx
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;; addq %rcx, %rdx
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;; xchgb %al, (%rdx)
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;; movzbq %al, %rax
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;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 4e: ud2

‎tests/disas/winch/x64/atomic/rmw/i64_atomic_rmw_xchg.wat

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@@ -0,0 +1,34 @@
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;;! target = "x86_64"
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;;! test = "winch"
3+
4+
(module
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(memory 1 1 shared)
6+
(func (export "_start") (result i64)
7+
(i64.atomic.rmw.xchg (i32.const 0) (i64.const 42))))
8+
;; wasm[0]::function[0]:
9+
;; pushq %rbp
10+
;; movq %rsp, %rbp
11+
;; movq 8(%rdi), %r11
12+
;; movq 0x10(%r11), %r11
13+
;; addq $0x10, %r11
14+
;; cmpq %rsp, %r11
15+
;; ja 0x5e
16+
;; 1c: movq %rdi, %r14
17+
;; subq $0x10, %rsp
18+
;; movq %rdi, 8(%rsp)
19+
;; movq %rsi, (%rsp)
20+
;; movq $0x2a, %rax
21+
;; movl $0, %ecx
22+
;; andq $7, %rcx
23+
;; cmpq $0, %rcx
24+
;; jne 0x60
25+
;; 46: movl $0, %ecx
26+
;; movq 0x58(%r14), %r11
27+
;; movq (%r11), %rdx
28+
;; addq %rcx, %rdx
29+
;; xchgq %rax, (%rdx)
30+
;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 5e: ud2
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;; 60: ud2

‎winch/codegen/src/isa/x64/asm.rs

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Original file line numberDiff line numberDiff line change
@@ -1147,6 +1147,31 @@ impl Assembler {
11471147
});
11481148
}
11491149

1150+
pub fn xchg(
1151+
&mut self,
1152+
addr: Address,
1153+
operand: Reg,
1154+
dst: WritableReg,
1155+
size: OperandSize,
1156+
flags: MemFlags,
1157+
) {
1158+
assert!(addr.is_offset());
1159+
let mem = Self::to_synthetic_amode(
1160+
&addr,
1161+
&mut self.pool,
1162+
&mut self.constants,
1163+
&mut self.buffer,
1164+
flags,
1165+
);
1166+
1167+
self.emit(Inst::Xchg {
1168+
size: size.into(),
1169+
operand: operand.into(),
1170+
mem,
1171+
dst_old: dst.map(Into::into),
1172+
});
1173+
}
1174+
11501175
pub fn cmp_ir(&mut self, src1: Reg, imm: i32, size: OperandSize) {
11511176
let imm = RegMemImm::imm(imm as u32);
11521177

‎winch/codegen/src/isa/x64/masm.rs

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Original file line numberDiff line numberDiff line change
@@ -1410,6 +1410,9 @@ impl Masm for MacroAssembler {
14101410
self.asm
14111411
.lock_xadd(addr, operand.to_reg(), operand, size, flags);
14121412
}
1413+
RmwOp::Xchg => {
1414+
self.asm.xchg(addr, operand.to_reg(), operand, size, flags);
1415+
}
14131416
}
14141417

14151418
if let Some(extend) = extend {

‎winch/codegen/src/masm.rs

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Original file line numberDiff line numberDiff line change
@@ -56,6 +56,7 @@ pub(crate) enum MulWideKind {
5656
pub(crate) enum RmwOp {
5757
Add,
5858
Sub,
59+
Xchg,
5960
}
6061

6162
/// The direction to perform the memory move.

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