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Commit 656a33e

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earlephilhowerearlephilhower
authoredMar 14, 2021
BREAKING - Use IRAM_ATTR in place of ICACHE_RAM_ATTR (#7921)
Update the core to use the define that the ESP32 uses, IRAM_ATTR, for placing code in DRAM.
1 parent 6743a65 commit 656a33e

26 files changed

+126
-126
lines changed
 

‎cores/esp8266/FunctionalInterrupt.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ typedef void (*voidFuncPtrArg)(void*);
1010
extern "C" void __attachInterruptFunctionalArg(uint8_t pin, voidFuncPtr userFunc, void*fp, int mode, bool functional);
1111

1212

13-
void ICACHE_RAM_ATTR interruptFunctional(void* arg)
13+
void IRAM_ATTR interruptFunctional(void* arg)
1414
{
1515
ArgStructure* localArg = (ArgStructure*)arg;
1616
if (localArg->functionInfo->reqScheduledFunction)

‎cores/esp8266/cbuf.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ size_t cbuf::resize(size_t newSize) {
6767
return _size;
6868
}
6969

70-
size_t ICACHE_RAM_ATTR cbuf::available() const {
70+
size_t IRAM_ATTR cbuf::available() const {
7171
if(_end >= _begin) {
7272
return _end - _begin;
7373
}
@@ -108,7 +108,7 @@ size_t cbuf::peek(char *dst, size_t size) {
108108
return size_read;
109109
}
110110

111-
int ICACHE_RAM_ATTR cbuf::read() {
111+
int IRAM_ATTR cbuf::read() {
112112
if(empty())
113113
return -1;
114114

@@ -133,7 +133,7 @@ size_t cbuf::read(char* dst, size_t size) {
133133
return size_read;
134134
}
135135

136-
size_t ICACHE_RAM_ATTR cbuf::write(char c) {
136+
size_t IRAM_ATTR cbuf::write(char c) {
137137
if(full())
138138
return 0;
139139

‎cores/esp8266/cont_util.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ void cont_init(cont_t* cont) {
4242
}
4343
}
4444

45-
int ICACHE_RAM_ATTR cont_check(cont_t* cont) {
45+
int IRAM_ATTR cont_check(cont_t* cont) {
4646
if(cont->stack_guard1 != CONT_STACKGUARD || cont->stack_guard2 != CONT_STACKGUARD) return 1;
4747

4848
return 0;
@@ -62,7 +62,7 @@ int cont_get_free_stack(cont_t* cont) {
6262
return freeWords * 4;
6363
}
6464

65-
bool ICACHE_RAM_ATTR cont_can_yield(cont_t* cont) {
65+
bool IRAM_ATTR cont_can_yield(cont_t* cont) {
6666
return !ETS_INTR_WITHINISR() &&
6767
cont->pc_ret != 0 && cont->pc_yield == 0;
6868
}

‎cores/esp8266/core_esp8266_i2s.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ typedef struct i2s_state {
6161
uint32_t * curr_slc_buf; // Current buffer for writing
6262
uint32_t curr_slc_buf_pos; // Position in the current buffer
6363
void (*callback) (void);
64-
// Callback function should be defined as 'void ICACHE_RAM_ATTR function_name()',
64+
// Callback function should be defined as 'void IRAM_ATTR function_name()',
6565
// and be placed in IRAM for faster execution. Avoid long computational tasks in this
6666
// function, use it to set flags and process later.
6767
bool driveClocks;
@@ -139,7 +139,7 @@ uint16_t i2s_rx_available(){
139139
}
140140

141141
// Pop the top off of the queue and return it
142-
static uint32_t * ICACHE_RAM_ATTR i2s_slc_queue_next_item(i2s_state_t *ch) {
142+
static uint32_t * IRAM_ATTR i2s_slc_queue_next_item(i2s_state_t *ch) {
143143
uint8_t i;
144144
uint32_t *item = ch->slc_queue[0];
145145
ch->slc_queue_len--;
@@ -150,7 +150,7 @@ static uint32_t * ICACHE_RAM_ATTR i2s_slc_queue_next_item(i2s_state_t *ch) {
150150
}
151151

152152
// Append an item to the end of the queue from receive
153-
static void ICACHE_RAM_ATTR i2s_slc_queue_append_item(i2s_state_t *ch, uint32_t *item) {
153+
static void IRAM_ATTR i2s_slc_queue_append_item(i2s_state_t *ch, uint32_t *item) {
154154
// Shift everything up, except for the one corresponding to this item
155155
for (int i=0, dest=0; i < ch->slc_queue_len; i++) {
156156
if (ch->slc_queue[i] != item) {
@@ -164,7 +164,7 @@ static void ICACHE_RAM_ATTR i2s_slc_queue_append_item(i2s_state_t *ch, uint32_t
164164
}
165165
}
166166

167-
static void ICACHE_RAM_ATTR i2s_slc_isr(void) {
167+
static void IRAM_ATTR i2s_slc_isr(void) {
168168
ETS_SLC_INTR_DISABLE();
169169
uint32_t slc_intr_status = SLCIS;
170170
SLCIC = 0xFFFFFFFF;

‎cores/esp8266/core_esp8266_phy.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -300,10 +300,10 @@ static const uint8_t ICACHE_FLASH_ATTR phy_init_data[128] =
300300
static bool spoof_init_data = false;
301301

302302
extern int __real_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size);
303-
extern int ICACHE_RAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size);
303+
extern int IRAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size);
304304
extern int __get_adc_mode();
305305

306-
extern int ICACHE_RAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size)
306+
extern int IRAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size)
307307
{
308308
if (!spoof_init_data || size != 128) {
309309
return __real_spi_flash_read(addr, dst, size);
@@ -354,6 +354,6 @@ void user_rf_pre_init()
354354
}
355355

356356

357-
void ICACHE_RAM_ATTR user_spi_flash_dio_to_qio_pre_init() {}
357+
void IRAM_ATTR user_spi_flash_dio_to_qio_pre_init() {}
358358

359359
};

‎cores/esp8266/core_esp8266_si2c.cpp

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -103,23 +103,23 @@ class Twi
103103
ETSTimer timer;
104104

105105
// Event/IRQ callbacks, so they can't use "this" and need to be static
106-
static void ICACHE_RAM_ATTR onSclChange(void);
107-
static void ICACHE_RAM_ATTR onSdaChange(void);
106+
static void IRAM_ATTR onSclChange(void);
107+
static void IRAM_ATTR onSdaChange(void);
108108
static void eventTask(ETSEvent *e);
109-
static void ICACHE_RAM_ATTR onTimer(void *unused);
109+
static void IRAM_ATTR onTimer(void *unused);
110110

111111
// Allow not linking in the slave code if there is no call to setAddress
112112
bool _slaveEnabled = false;
113113

114114
// Internal use functions
115-
void ICACHE_RAM_ATTR busywait(unsigned int v);
115+
void IRAM_ATTR busywait(unsigned int v);
116116
bool write_start(void);
117117
bool write_stop(void);
118118
bool write_bit(bool bit);
119119
bool read_bit(void);
120120
bool write_byte(unsigned char byte);
121121
unsigned char read_byte(bool nack);
122-
void ICACHE_RAM_ATTR onTwipEvent(uint8_t status);
122+
void IRAM_ATTR onTwipEvent(uint8_t status);
123123

124124
// Handle the case where a slave needs to stretch the clock with a time-limited busy wait
125125
inline void WAIT_CLOCK_STRETCH()
@@ -149,8 +149,8 @@ class Twi
149149
uint8_t transmit(const uint8_t* data, uint8_t length);
150150
void attachSlaveRxEvent(void (*function)(uint8_t*, size_t));
151151
void attachSlaveTxEvent(void (*function)(void));
152-
void ICACHE_RAM_ATTR reply(uint8_t ack);
153-
void ICACHE_RAM_ATTR releaseBus(void);
152+
void IRAM_ATTR reply(uint8_t ack);
153+
void IRAM_ATTR releaseBus(void);
154154
void enableSlave();
155155
};
156156

@@ -229,7 +229,7 @@ void Twi::enableSlave()
229229
}
230230
}
231231

232-
void ICACHE_RAM_ATTR Twi::busywait(unsigned int v)
232+
void IRAM_ATTR Twi::busywait(unsigned int v)
233233
{
234234
unsigned int i;
235235
for (i = 0; i < v; i++) // loop time is 5 machine cycles: 31.25ns @ 160MHz, 62.5ns @ 80MHz
@@ -472,9 +472,9 @@ void Twi::attachSlaveTxEvent(void (*function)(void))
472472
}
473473

474474
// DO NOT INLINE, inlining reply() in combination with compiler optimizations causes function breakup into
475-
// parts and the ICACHE_RAM_ATTR isn't propagated correctly to all parts, which of course causes crashes.
475+
// parts and the IRAM_ATTR isn't propagated correctly to all parts, which of course causes crashes.
476476
// TODO: test with gcc 9.x and if it still fails, disable optimization with -fdisable-ipa-fnsplit
477-
void ICACHE_RAM_ATTR Twi::reply(uint8_t ack)
477+
void IRAM_ATTR Twi::reply(uint8_t ack)
478478
{
479479
// transmit master read ready signal, with or without ack
480480
if (ack)
@@ -492,7 +492,7 @@ void ICACHE_RAM_ATTR Twi::reply(uint8_t ack)
492492
}
493493

494494

495-
void ICACHE_RAM_ATTR Twi::releaseBus(void)
495+
void IRAM_ATTR Twi::releaseBus(void)
496496
{
497497
// release bus
498498
//TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA) | _BV(TWINT);
@@ -505,7 +505,7 @@ void ICACHE_RAM_ATTR Twi::releaseBus(void)
505505
}
506506

507507

508-
void ICACHE_RAM_ATTR Twi::onTwipEvent(uint8_t status)
508+
void IRAM_ATTR Twi::onTwipEvent(uint8_t status)
509509
{
510510
twip_status = status;
511511
switch (status)
@@ -612,7 +612,7 @@ void ICACHE_RAM_ATTR Twi::onTwipEvent(uint8_t status)
612612
}
613613
}
614614

615-
void ICACHE_RAM_ATTR Twi::onTimer(void *unused)
615+
void IRAM_ATTR Twi::onTimer(void *unused)
616616
{
617617
(void)unused;
618618
twi.releaseBus();
@@ -662,7 +662,7 @@ void Twi::eventTask(ETSEvent *e)
662662
// Shorthand for if the state is any of the or'd bitmask x
663663
#define IFSTATE(x) if (twip_state_mask & (x))
664664

665-
void ICACHE_RAM_ATTR Twi::onSclChange(void)
665+
void IRAM_ATTR Twi::onSclChange(void)
666666
{
667667
unsigned int sda;
668668
unsigned int scl;
@@ -860,7 +860,7 @@ void ICACHE_RAM_ATTR Twi::onSclChange(void)
860860
}
861861
}
862862

863-
void ICACHE_RAM_ATTR Twi::onSdaChange(void)
863+
void IRAM_ATTR Twi::onSdaChange(void)
864864
{
865865
unsigned int sda;
866866
unsigned int scl;

‎cores/esp8266/core_esp8266_timer.cpp

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ extern "C" {
3131

3232
static volatile timercallback timer1_user_cb = NULL;
3333

34-
void ICACHE_RAM_ATTR timer1_isr_handler(void *para, void *frame) {
34+
void IRAM_ATTR timer1_isr_handler(void *para, void *frame) {
3535
(void) para;
3636
(void) frame;
3737
if ((T1C & ((1 << TCAR) | (1 << TCIT))) == 0) TEIE &= ~TEIE1;//edge int disable
@@ -45,32 +45,32 @@ void ICACHE_RAM_ATTR timer1_isr_handler(void *para, void *frame) {
4545
}
4646
}
4747

48-
void ICACHE_RAM_ATTR timer1_isr_init(){
48+
void IRAM_ATTR timer1_isr_init(){
4949
ETS_FRC_TIMER1_INTR_ATTACH(timer1_isr_handler, NULL);
5050
}
5151

52-
void ICACHE_RAM_ATTR timer1_attachInterrupt(timercallback userFunc) {
52+
void IRAM_ATTR timer1_attachInterrupt(timercallback userFunc) {
5353
timer1_user_cb = userFunc;
5454
ETS_FRC1_INTR_ENABLE();
5555
}
5656

57-
void ICACHE_RAM_ATTR timer1_detachInterrupt() {
57+
void IRAM_ATTR timer1_detachInterrupt() {
5858
timer1_user_cb = 0;
5959
TEIE &= ~TEIE1;//edge int disable
6060
ETS_FRC1_INTR_DISABLE();
6161
}
6262

63-
void ICACHE_RAM_ATTR timer1_enable(uint8_t divider, uint8_t int_type, uint8_t reload){
63+
void IRAM_ATTR timer1_enable(uint8_t divider, uint8_t int_type, uint8_t reload){
6464
T1C = (1 << TCTE) | ((divider & 3) << TCPD) | ((int_type & 1) << TCIT) | ((reload & 1) << TCAR);
6565
T1I = 0;
6666
}
6767

68-
void ICACHE_RAM_ATTR timer1_write(uint32_t ticks){
68+
void IRAM_ATTR timer1_write(uint32_t ticks){
6969
T1L = ((ticks)& 0x7FFFFF);
7070
if ((T1C & (1 << TCIT)) == 0) TEIE |= TEIE1;//edge int enable
7171
}
7272

73-
void ICACHE_RAM_ATTR timer1_disable(){
73+
void IRAM_ATTR timer1_disable(){
7474
T1C = 0;
7575
T1I = 0;
7676
}
@@ -80,7 +80,7 @@ void ICACHE_RAM_ATTR timer1_disable(){
8080

8181
static volatile timercallback timer0_user_cb = NULL;
8282

83-
void ICACHE_RAM_ATTR timer0_isr_handler(void *para, void *frame) {
83+
void IRAM_ATTR timer0_isr_handler(void *para, void *frame) {
8484
(void) para;
8585
(void) frame;
8686
if (timer0_user_cb) {
@@ -92,16 +92,16 @@ void ICACHE_RAM_ATTR timer0_isr_handler(void *para, void *frame) {
9292
}
9393
}
9494

95-
void ICACHE_RAM_ATTR timer0_isr_init(){
95+
void IRAM_ATTR timer0_isr_init(){
9696
ETS_CCOMPARE0_INTR_ATTACH(timer0_isr_handler, NULL);
9797
}
9898

99-
void ICACHE_RAM_ATTR timer0_attachInterrupt(timercallback userFunc) {
99+
void IRAM_ATTR timer0_attachInterrupt(timercallback userFunc) {
100100
timer0_user_cb = userFunc;
101101
ETS_CCOMPARE0_ENABLE();
102102
}
103103

104-
void ICACHE_RAM_ATTR timer0_detachInterrupt() {
104+
void IRAM_ATTR timer0_detachInterrupt() {
105105
timer0_user_cb = NULL;
106106
ETS_CCOMPARE0_DISABLE();
107107
}

‎cores/esp8266/core_esp8266_waveform.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ int stopWaveform(uint8_t pin);
112112
// to determine whether or not to perform an operation.
113113
// Pass in NULL to disable the callback and, if no other waveforms being
114114
// generated, stop the timer as well.
115-
// Make sure the CB function has the ICACHE_RAM_ATTR decorator.
115+
// Make sure the CB function has the IRAM_ATTR decorator.
116116
void setTimer1Callback(uint32_t (*fn)());
117117

118118

‎cores/esp8266/core_esp8266_waveform_phase.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,7 @@ namespace {
111111
}
112112

113113
// Interrupt on/off control
114-
static ICACHE_RAM_ATTR void timer1Interrupt();
114+
static IRAM_ATTR void timer1Interrupt();
115115

116116
// Non-speed critical bits
117117
#pragma GCC optimize ("Os")
@@ -125,7 +125,7 @@ static void initTimer() {
125125
timer1_write(IRQLATENCYCCYS); // Cause an interrupt post-haste
126126
}
127127

128-
static void ICACHE_RAM_ATTR deinitTimer() {
128+
static void IRAM_ATTR deinitTimer() {
129129
ETS_FRC_TIMER1_NMI_INTR_ATTACH(NULL);
130130
timer1_disable();
131131
timer1_isr_init();
@@ -218,7 +218,7 @@ int startWaveformClockCycles_weak(uint8_t pin, uint32_t highCcys, uint32_t lowCc
218218
}
219219

220220
// Stops a waveform on a pin
221-
ICACHE_RAM_ATTR int stopWaveform_weak(uint8_t pin) {
221+
IRAM_ATTR int stopWaveform_weak(uint8_t pin) {
222222
// Can't possibly need to stop anything if there is no timer active
223223
if (!waveform.timer1Running) {
224224
return false;
@@ -252,7 +252,7 @@ ICACHE_RAM_ATTR int stopWaveform_weak(uint8_t pin) {
252252

253253
// For dynamic CPU clock frequency switch in loop the scaling logic would have to be adapted.
254254
// Using constexpr makes sure that the CPU clock frequency is compile-time fixed.
255-
static inline ICACHE_RAM_ATTR int32_t scaleCcys(const int32_t ccys, const bool isCPU2X) {
255+
static inline IRAM_ATTR int32_t scaleCcys(const int32_t ccys, const bool isCPU2X) {
256256
if (ISCPUFREQ160MHZ) {
257257
return isCPU2X ? ccys : (ccys >> 1);
258258
}
@@ -261,7 +261,7 @@ static inline ICACHE_RAM_ATTR int32_t scaleCcys(const int32_t ccys, const bool i
261261
}
262262
}
263263

264-
static ICACHE_RAM_ATTR void timer1Interrupt() {
264+
static IRAM_ATTR void timer1Interrupt() {
265265
const uint32_t isrStartCcy = ESP.getCycleCount();
266266
int32_t clockDrift = isrStartCcy - waveform.nextEventCcy;
267267
const bool isCPU2X = CPU2X & 1;

‎cores/esp8266/core_esp8266_waveform_pwm.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ static WVFState wvfState;
9393
#pragma GCC optimize ("Os")
9494

9595
// Interrupt on/off control
96-
static ICACHE_RAM_ATTR void timer1Interrupt();
96+
static IRAM_ATTR void timer1Interrupt();
9797
static bool timerRunning = false;
9898

9999
static __attribute__((noinline)) void initTimer() {
@@ -107,7 +107,7 @@ static __attribute__((noinline)) void initTimer() {
107107
}
108108
}
109109

110-
static ICACHE_RAM_ATTR void forceTimerInterrupt() {
110+
static IRAM_ATTR void forceTimerInterrupt() {
111111
if (T1L > microsecondsToClockCycles(10)) {
112112
T1L = microsecondsToClockCycles(10);
113113
}
@@ -144,7 +144,7 @@ static uint32_t _pwmPeriod = microsecondsToClockCycles(1000000UL) / _pwmFreq;
144144

145145
// If there are no more scheduled activities, shut down Timer 1.
146146
// Otherwise, do nothing.
147-
static ICACHE_RAM_ATTR void disableIdleTimer() {
147+
static IRAM_ATTR void disableIdleTimer() {
148148
if (timerRunning && !wvfState.waveformEnabled && !pwmState.cnt && !wvfState.timer1CB) {
149149
ETS_FRC_TIMER1_NMI_INTR_ATTACH(NULL);
150150
timer1_disable();
@@ -155,7 +155,7 @@ static ICACHE_RAM_ATTR void disableIdleTimer() {
155155

156156
// Notify the NMI that a new PWM state is available through the mailbox.
157157
// Wait for mailbox to be emptied (either busy or delay() as needed)
158-
static ICACHE_RAM_ATTR void _notifyPWM(PWMState *p, bool idle) {
158+
static IRAM_ATTR void _notifyPWM(PWMState *p, bool idle) {
159159
p->pwmUpdate = nullptr;
160160
pwmState.pwmUpdate = p;
161161
MEMBARRIER();
@@ -237,7 +237,7 @@ static void _cleanAndRemovePWM(PWMState *p, int pin) {
237237

238238
// Disable PWM on a specific pin (i.e. when a digitalWrite or analogWrite(0%/100%))
239239
extern bool _stopPWM_weak(uint8_t pin) __attribute__((weak));
240-
ICACHE_RAM_ATTR bool _stopPWM_weak(uint8_t pin) {
240+
IRAM_ATTR bool _stopPWM_weak(uint8_t pin) {
241241
if (!((1<<pin) & pwmState.mask)) {
242242
return false; // Pin not actually active
243243
}
@@ -430,7 +430,7 @@ void setTimer1Callback(uint32_t (*fn)()) {
430430

431431
// Stops a waveform on a pin
432432
extern int stopWaveform_weak(uint8_t pin) __attribute__((weak));
433-
ICACHE_RAM_ATTR int stopWaveform_weak(uint8_t pin) {
433+
IRAM_ATTR int stopWaveform_weak(uint8_t pin) {
434434
// Can't possibly need to stop anything if there is no timer active
435435
if (!timerRunning) {
436436
return false;
@@ -454,7 +454,7 @@ ICACHE_RAM_ATTR int stopWaveform_weak(uint8_t pin) {
454454
return true;
455455
}
456456
static int stopWaveform_bound(uint8_t pin) __attribute__((weakref("stopWaveform_weak")));
457-
ICACHE_RAM_ATTR int stopWaveform(uint8_t pin) {
457+
IRAM_ATTR int stopWaveform(uint8_t pin) {
458458
return stopWaveform_bound(pin);
459459
}
460460

@@ -464,14 +464,14 @@ ICACHE_RAM_ATTR int stopWaveform(uint8_t pin) {
464464
// Normally would not want two copies like this, but due to different
465465
// optimization levels the inline attribute gets lost if we try the
466466
// other version.
467-
static inline ICACHE_RAM_ATTR uint32_t GetCycleCountIRQ() {
467+
static inline IRAM_ATTR uint32_t GetCycleCountIRQ() {
468468
uint32_t ccount;
469469
__asm__ __volatile__("rsr %0,ccount":"=a"(ccount));
470470
return ccount;
471471
}
472472

473473
// Find the earliest cycle as compared to right now
474-
static inline ICACHE_RAM_ATTR uint32_t earliest(uint32_t a, uint32_t b) {
474+
static inline IRAM_ATTR uint32_t earliest(uint32_t a, uint32_t b) {
475475
uint32_t now = GetCycleCountIRQ();
476476
int32_t da = a - now;
477477
int32_t db = b - now;
@@ -496,7 +496,7 @@ static inline ICACHE_RAM_ATTR uint32_t earliest(uint32_t a, uint32_t b) {
496496
// When the time to the next edge is greater than this, RTI and set another IRQ to minimize CPU usage
497497
#define MINIRQTIME microsecondsToClockCycles(4)
498498

499-
static ICACHE_RAM_ATTR void timer1Interrupt() {
499+
static IRAM_ATTR void timer1Interrupt() {
500500
// Flag if the core is at 160 MHz, for use by adjust()
501501
bool turbo = (*(uint32_t*)0x3FF00014) & 1 ? true : false;
502502

‎cores/esp8266/core_esp8266_wiring.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ void micros_overflow_tick(void* arg) {
149149
//
150150
// Reference function: corrected millis(), 64-bit arithmetic,
151151
// truncated to 32-bits by return
152-
// unsigned long ICACHE_RAM_ATTR millis_corr_DEBUG( void )
152+
// unsigned long IRAM_ATTR millis_corr_DEBUG( void )
153153
// {
154154
// // Get usec system time, usec overflow conter
155155
// ......
@@ -163,7 +163,7 @@ void micros_overflow_tick(void* arg) {
163163
#define MAGIC_1E3_wLO 0x4bc6a7f0 // LS part
164164
#define MAGIC_1E3_wHI 0x00418937 // MS part, magic multiplier
165165

166-
unsigned long ICACHE_RAM_ATTR millis()
166+
unsigned long IRAM_ATTR millis()
167167
{
168168
union {
169169
uint64_t q; // Accumulator, 64-bit, little endian
@@ -194,18 +194,18 @@ unsigned long ICACHE_RAM_ATTR millis()
194194

195195
} //millis
196196

197-
unsigned long ICACHE_RAM_ATTR micros() {
197+
unsigned long IRAM_ATTR micros() {
198198
return system_get_time();
199199
}
200200

201-
uint64_t ICACHE_RAM_ATTR micros64() {
201+
uint64_t IRAM_ATTR micros64() {
202202
uint32_t low32_us = system_get_time();
203203
uint32_t high32_us = micros_overflow_count + ((low32_us < micros_at_last_overflow_tick) ? 1 : 0);
204204
uint64_t duration64_us = (uint64_t)high32_us << 32 | low32_us;
205205
return duration64_us;
206206
}
207207

208-
void ICACHE_RAM_ATTR delayMicroseconds(unsigned int us) {
208+
void IRAM_ATTR delayMicroseconds(unsigned int us) {
209209
os_delay_us(us);
210210
}
211211

‎cores/esp8266/core_esp8266_wiring_digital.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@ extern void __pinMode(uint8_t pin, uint8_t mode) {
8181
}
8282
}
8383

84-
extern void ICACHE_RAM_ATTR __digitalWrite(uint8_t pin, uint8_t val) {
84+
extern void IRAM_ATTR __digitalWrite(uint8_t pin, uint8_t val) {
8585
stopWaveform(pin); // Disable any Tone or startWaveform on this pin
8686
_stopPWM(pin); // and any analogWrites (PWM)
8787
if(pin < 16){
@@ -93,7 +93,7 @@ extern void ICACHE_RAM_ATTR __digitalWrite(uint8_t pin, uint8_t val) {
9393
}
9494
}
9595

96-
extern int ICACHE_RAM_ATTR __digitalRead(uint8_t pin) {
96+
extern int IRAM_ATTR __digitalRead(uint8_t pin) {
9797
if(pin < 16){
9898
return GPIP(pin);
9999
} else if(pin == 16){
@@ -131,7 +131,7 @@ typedef struct {
131131
static interrupt_handler_t interrupt_handlers[16] = { {0, 0, 0, 0}, };
132132
static uint32_t interrupt_reg = 0;
133133

134-
void ICACHE_RAM_ATTR interrupt_handler(void *arg, void *frame)
134+
void IRAM_ATTR interrupt_handler(void *arg, void *frame)
135135
{
136136
(void) arg;
137137
(void) frame;
@@ -218,7 +218,7 @@ extern void __attachInterruptArg(uint8_t pin, voidFuncPtrArg userFunc, void* arg
218218
__attachInterruptFunctionalArg(pin, userFunc, arg, mode, false);
219219
}
220220

221-
extern void ICACHE_RAM_ATTR __detachInterrupt(uint8_t pin) {
221+
extern void IRAM_ATTR __detachInterrupt(uint8_t pin) {
222222
if (pin < 16)
223223
{
224224
ETS_GPIO_INTR_DISABLE();

‎cores/esp8266/gdb_hooks.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
same stub can be used for gdb_present. */
2727
extern "C" {
2828

29-
static bool ICACHE_RAM_ATTR __gdb_no_op()
29+
static bool IRAM_ATTR __gdb_no_op()
3030
{
3131
return false;
3232
}

‎cores/esp8266/heap.cpp

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,7 @@ void* _calloc_r(struct _reent* unused, size_t count, size_t size)
164164

165165
#define DEBUG_HEAP_PRINTF ets_uart_printf
166166

167-
void ICACHE_RAM_ATTR print_loc(size_t size, const char* file, int line)
167+
void IRAM_ATTR print_loc(size_t size, const char* file, int line)
168168
{
169169
(void)size;
170170
(void)line;
@@ -186,7 +186,7 @@ void ICACHE_RAM_ATTR print_loc(size_t size, const char* file, int line)
186186
}
187187
}
188188

189-
void ICACHE_RAM_ATTR print_oom_size(size_t size)
189+
void IRAM_ATTR print_oom_size(size_t size)
190190
{
191191
(void)size;
192192
if (system_get_os_print()) {
@@ -232,7 +232,7 @@ void ICACHE_RAM_ATTR print_oom_size(size_t size)
232232
For malloc(), calloc(), and zalloc() Full Posion Check is done 1st since
233233
these functions do not modify an existing allocation.
234234
*/
235-
void* ICACHE_RAM_ATTR malloc(size_t size)
235+
void* IRAM_ATTR malloc(size_t size)
236236
{
237237
INTEGRITY_CHECK__ABORT();
238238
POISON_CHECK__ABORT();
@@ -242,7 +242,7 @@ void* ICACHE_RAM_ATTR malloc(size_t size)
242242
return ret;
243243
}
244244

245-
void* ICACHE_RAM_ATTR calloc(size_t count, size_t size)
245+
void* IRAM_ATTR calloc(size_t count, size_t size)
246246
{
247247
INTEGRITY_CHECK__ABORT();
248248
POISON_CHECK__ABORT();
@@ -252,7 +252,7 @@ void* ICACHE_RAM_ATTR calloc(size_t count, size_t size)
252252
return ret;
253253
}
254254

255-
void* ICACHE_RAM_ATTR realloc(void* ptr, size_t size)
255+
void* IRAM_ATTR realloc(void* ptr, size_t size)
256256
{
257257
INTEGRITY_CHECK__ABORT();
258258
void* ret = UMM_REALLOC_FL(ptr, size, NULL, 0);
@@ -262,7 +262,7 @@ void* ICACHE_RAM_ATTR realloc(void* ptr, size_t size)
262262
return ret;
263263
}
264264

265-
void ICACHE_RAM_ATTR free(void* p)
265+
void IRAM_ATTR free(void* p)
266266
{
267267
INTEGRITY_CHECK__ABORT();
268268
UMM_FREE_FL(p, NULL, 0);
@@ -271,7 +271,7 @@ void ICACHE_RAM_ATTR free(void* p)
271271
#endif
272272

273273
STATIC_ALWAYS_INLINE
274-
void* ICACHE_RAM_ATTR heap_pvPortMalloc(size_t size, const char* file, int line)
274+
void* IRAM_ATTR heap_pvPortMalloc(size_t size, const char* file, int line)
275275
{
276276
INTEGRITY_CHECK__PANIC_FL(file, line);
277277
POISON_CHECK__PANIC_FL(file, line);
@@ -282,7 +282,7 @@ void* ICACHE_RAM_ATTR heap_pvPortMalloc(size_t size, const char* file, int line)
282282
}
283283

284284
STATIC_ALWAYS_INLINE
285-
void* ICACHE_RAM_ATTR heap_pvPortCalloc(size_t count, size_t size, const char* file, int line)
285+
void* IRAM_ATTR heap_pvPortCalloc(size_t count, size_t size, const char* file, int line)
286286
{
287287
INTEGRITY_CHECK__PANIC_FL(file, line);
288288
POISON_CHECK__PANIC_FL(file, line);
@@ -293,7 +293,7 @@ void* ICACHE_RAM_ATTR heap_pvPortCalloc(size_t count, size_t size, const char* f
293293
}
294294

295295
STATIC_ALWAYS_INLINE
296-
void* ICACHE_RAM_ATTR heap_pvPortRealloc(void *ptr, size_t size, const char* file, int line)
296+
void* IRAM_ATTR heap_pvPortRealloc(void *ptr, size_t size, const char* file, int line)
297297
{
298298
INTEGRITY_CHECK__PANIC_FL(file, line);
299299
void* ret = UMM_REALLOC_FL(ptr, size, file, line);
@@ -304,7 +304,7 @@ void* ICACHE_RAM_ATTR heap_pvPortRealloc(void *ptr, size_t size, const char* fil
304304
}
305305

306306
STATIC_ALWAYS_INLINE
307-
void* ICACHE_RAM_ATTR heap_pvPortZalloc(size_t size, const char* file, int line)
307+
void* IRAM_ATTR heap_pvPortZalloc(size_t size, const char* file, int line)
308308
{
309309
INTEGRITY_CHECK__PANIC_FL(file, line);
310310
POISON_CHECK__PANIC_FL(file, line);
@@ -315,14 +315,14 @@ void* ICACHE_RAM_ATTR heap_pvPortZalloc(size_t size, const char* file, int line)
315315
}
316316

317317
STATIC_ALWAYS_INLINE
318-
void ICACHE_RAM_ATTR heap_vPortFree(void *ptr, const char* file, int line)
318+
void IRAM_ATTR heap_vPortFree(void *ptr, const char* file, int line)
319319
{
320320
INTEGRITY_CHECK__PANIC_FL(file, line);
321321
UMM_FREE_FL(ptr, file, line);
322322
POISON_CHECK__PANIC_FL(file, line);
323323
}
324324

325-
size_t ICACHE_RAM_ATTR xPortWantedSizeAlign(size_t size)
325+
size_t IRAM_ATTR xPortWantedSizeAlign(size_t size)
326326
{
327327
return (size + 3) & ~((size_t) 3);
328328
}
@@ -338,31 +338,31 @@ void system_show_malloc(void)
338338
malloc calls pvPortMalloc, ... we can leverage that for this solution.
339339
Force pvPortMalloc, ... APIs to serve DRAM only.
340340
*/
341-
void* ICACHE_RAM_ATTR pvPortMalloc(size_t size, const char* file, int line)
341+
void* IRAM_ATTR pvPortMalloc(size_t size, const char* file, int line)
342342
{
343343
HeapSelectDram ephemeral;
344344
return heap_pvPortMalloc(size, file, line);;
345345
}
346346

347-
void* ICACHE_RAM_ATTR pvPortCalloc(size_t count, size_t size, const char* file, int line)
347+
void* IRAM_ATTR pvPortCalloc(size_t count, size_t size, const char* file, int line)
348348
{
349349
HeapSelectDram ephemeral;
350350
return heap_pvPortCalloc(count, size, file, line);
351351
}
352352

353-
void* ICACHE_RAM_ATTR pvPortRealloc(void *ptr, size_t size, const char* file, int line)
353+
void* IRAM_ATTR pvPortRealloc(void *ptr, size_t size, const char* file, int line)
354354
{
355355
HeapSelectDram ephemeral;
356356
return heap_pvPortRealloc(ptr, size, file, line);
357357
}
358358

359-
void* ICACHE_RAM_ATTR pvPortZalloc(size_t size, const char* file, int line)
359+
void* IRAM_ATTR pvPortZalloc(size_t size, const char* file, int line)
360360
{
361361
HeapSelectDram ephemeral;
362362
return heap_pvPortZalloc(size, file, line);
363363
}
364364

365-
void ICACHE_RAM_ATTR vPortFree(void *ptr, const char* file, int line)
365+
void IRAM_ATTR vPortFree(void *ptr, const char* file, int line)
366366
{
367367
#if defined(DEBUG_ESP_OOM) || defined(UMM_POISON_CHECK) || defined(UMM_POISON_CHECK_LITE) || defined(UMM_INTEGRITY_CHECK)
368368
// This is only needed for debug checks to ensure they are performed in

‎cores/esp8266/libc_replacements.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -47,43 +47,43 @@
4747

4848
extern "C" {
4949

50-
int ICACHE_RAM_ATTR _open_r (struct _reent* unused, const char *ptr, int mode) {
50+
int IRAM_ATTR _open_r (struct _reent* unused, const char *ptr, int mode) {
5151
(void)unused;
5252
(void)ptr;
5353
(void)mode;
5454
return 0;
5555
}
5656

57-
int ICACHE_RAM_ATTR _close_r(struct _reent* unused, int file) {
57+
int IRAM_ATTR _close_r(struct _reent* unused, int file) {
5858
(void)unused;
5959
(void)file;
6060
return 0;
6161
}
6262

63-
int ICACHE_RAM_ATTR _fstat_r(struct _reent* unused, int file, struct stat *st) {
63+
int IRAM_ATTR _fstat_r(struct _reent* unused, int file, struct stat *st) {
6464
(void)unused;
6565
(void)file;
6666
st->st_mode = S_IFCHR;
6767
return 0;
6868
}
6969

70-
int ICACHE_RAM_ATTR _lseek_r(struct _reent* unused, int file, int ptr, int dir) {
70+
int IRAM_ATTR _lseek_r(struct _reent* unused, int file, int ptr, int dir) {
7171
(void)unused;
7272
(void)file;
7373
(void)ptr;
7474
(void)dir;
7575
return 0;
7676
}
7777

78-
int ICACHE_RAM_ATTR _read_r(struct _reent* unused, int file, char *ptr, int len) {
78+
int IRAM_ATTR _read_r(struct _reent* unused, int file, char *ptr, int len) {
7979
(void)unused;
8080
(void)file;
8181
(void)ptr;
8282
(void)len;
8383
return 0;
8484
}
8585

86-
int ICACHE_RAM_ATTR _write_r(struct _reent* r, int file, char *ptr, int len) {
86+
int IRAM_ATTR _write_r(struct _reent* r, int file, char *ptr, int len) {
8787
(void) r;
8888
int pos = len;
8989
if (file == STDOUT_FILENO) {
@@ -95,9 +95,9 @@ int ICACHE_RAM_ATTR _write_r(struct _reent* r, int file, char *ptr, int len) {
9595
return len;
9696
}
9797

98-
int ICACHE_RAM_ATTR _putc_r(struct _reent* r, int c, FILE* file) __attribute__((weak));
98+
int IRAM_ATTR _putc_r(struct _reent* r, int c, FILE* file) __attribute__((weak));
9999

100-
int ICACHE_RAM_ATTR _putc_r(struct _reent* r, int c, FILE* file) {
100+
int IRAM_ATTR _putc_r(struct _reent* r, int c, FILE* file) {
101101
(void) r;
102102
if (file->_file == STDOUT_FILENO) {
103103
ets_putc(c);
@@ -106,7 +106,7 @@ int ICACHE_RAM_ATTR _putc_r(struct _reent* r, int c, FILE* file) {
106106
return EOF;
107107
}
108108

109-
int ICACHE_RAM_ATTR puts(const char * str) {
109+
int IRAM_ATTR puts(const char * str) {
110110
char c;
111111
while((c = *str) != 0) {
112112
ets_putc(c);
@@ -117,7 +117,7 @@ int ICACHE_RAM_ATTR puts(const char * str) {
117117
}
118118

119119
#undef putchar
120-
int ICACHE_RAM_ATTR putchar(int c) {
120+
int IRAM_ATTR putchar(int c) {
121121
ets_putc(c);
122122
return c;
123123
}

‎cores/esp8266/reboot_uart_dwnld.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ static inline void __wsr_vecbase(uint32_t vector_base) {
5252
asm volatile("wsr.vecbase %0" :: "r" (vector_base));
5353
}
5454

55-
[[noreturn]] void ICACHE_RAM_ATTR esp8266UartDownloadMode()
55+
[[noreturn]] void IRAM_ATTR esp8266UartDownloadMode()
5656
{
5757
/* reverse engineered from system_restart_core() */
5858
/* Before disabling instruction cache and restoring instruction RAM to a

‎cores/esp8266/uart.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ struct uart_
115115

116116

117117
// called by ISR
118-
inline size_t ICACHE_RAM_ATTR
118+
inline size_t IRAM_ATTR
119119
uart_rx_fifo_available(const int uart_nr)
120120
{
121121
return (USS(uart_nr) >> USRXC) & 0xFF;
@@ -144,7 +144,7 @@ uart_rx_available_unsafe(uart_t* uart)
144144

145145
// Copy all the rx fifo bytes that fit into the rx buffer
146146
// called by ISR
147-
inline void ICACHE_RAM_ATTR
147+
inline void IRAM_ATTR
148148
uart_rx_copy_fifo_to_buffer_unsafe(uart_t* uart)
149149
{
150150
struct uart_rx_buffer_ *rx_buffer = uart->rx_buffer;
@@ -289,7 +289,7 @@ uart_read(uart_t* uart, char* userbuffer, size_t usersize)
289289
// instead of the uart_isr...uart_rx_copy_fifo_to_buffer_unsafe()
290290
// Since we've already read the bytes from the FIFO, can't use that
291291
// function directly and need to implement it bytewise here
292-
static void ICACHE_RAM_ATTR uart_isr_handle_data(void* arg, uint8_t data)
292+
static void IRAM_ATTR uart_isr_handle_data(void* arg, uint8_t data)
293293
{
294294
uart_t* uart = (uart_t*)arg;
295295
if(uart == NULL || !uart->rx_enabled) {
@@ -370,7 +370,7 @@ uart_get_rx_buffer_size(uart_t* uart)
370370
}
371371

372372
// The default ISR handler called when GDB is not enabled
373-
void ICACHE_RAM_ATTR
373+
void IRAM_ATTR
374374
uart_isr(void * arg, void * frame)
375375
{
376376
(void) frame;

‎cores/esp8266/umm_malloc/umm_malloc_cfg.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -793,11 +793,11 @@ extern "C" {
793793
#include <pgmspace.h>
794794
// Reuse pvPort* calls, since they already support passing location information.
795795
// Specificly the debug version (heap_...) that does not force DRAM heap.
796-
void* ICACHE_RAM_ATTR heap_pvPortMalloc(size_t size, const char* file, int line);
797-
void* ICACHE_RAM_ATTR heap_pvPortCalloc(size_t count, size_t size, const char* file, int line);
798-
void* ICACHE_RAM_ATTR heap_pvPortRealloc(void *ptr, size_t size, const char* file, int line);
799-
void* ICACHE_RAM_ATTR heap_pvPortZalloc(size_t size, const char* file, int line);
800-
void ICACHE_RAM_ATTR heap_vPortFree(void *ptr, const char* file, int line);
796+
void* IRAM_ATTR heap_pvPortMalloc(size_t size, const char* file, int line);
797+
void* IRAM_ATTR heap_pvPortCalloc(size_t count, size_t size, const char* file, int line);
798+
void* IRAM_ATTR heap_pvPortRealloc(void *ptr, size_t size, const char* file, int line);
799+
void* IRAM_ATTR heap_pvPortZalloc(size_t size, const char* file, int line);
800+
void IRAM_ATTR heap_vPortFree(void *ptr, const char* file, int line);
801801

802802
#define malloc(s) ({ static const char mem_debug_file[] PROGMEM STORE_ATTR = __FILE__; heap_pvPortMalloc(s, mem_debug_file, __LINE__); })
803803
#define calloc(n,s) ({ static const char mem_debug_file[] PROGMEM STORE_ATTR = __FILE__; heap_pvPortCalloc(n, s, mem_debug_file, __LINE__); })
@@ -811,10 +811,10 @@ void ICACHE_RAM_ATTR heap_vPortFree(void *ptr, const char* file, int line);
811811

812812
#elif defined(UMM_POISON_CHECK) || defined(UMM_POISON_CHECK_LITE)
813813
#include <pgmspace.h>
814-
void* ICACHE_RAM_ATTR heap_pvPortRealloc(void *ptr, size_t size, const char* file, int line);
814+
void* IRAM_ATTR heap_pvPortRealloc(void *ptr, size_t size, const char* file, int line);
815815
#define realloc(p,s) ({ static const char mem_debug_file[] PROGMEM STORE_ATTR = __FILE__; heap_pvPortRealloc(p, s, mem_debug_file, __LINE__); })
816816

817-
void ICACHE_RAM_ATTR heap_vPortFree(void *ptr, const char* file, int line);
817+
void IRAM_ATTR heap_vPortFree(void *ptr, const char* file, int line);
818818
//C - to be discussed
819819
/*
820820
Problem, I would like to report the file and line number with the umm poison

‎doc/faq/a02-my-esp-crashes.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -247,8 +247,8 @@ Interrupt Service Routines
247247
cache may kick in for that code. However, the cache currently can't be used
248248
during hardware interrupts. That means that, if you use a hardware ISR, such as
249249
attachInterrupt(gpio, myISR, CHANGE) for a GPIO change, the ISR must have the
250-
ICACHE_RAM_ATTR attribute declared. Not only that, but the entire function tree
251-
called from the ISR must also have the ICACHE_RAM_ATTR declared.
250+
IRAM_ATTR attribute declared. Not only that, but the entire function tree
251+
called from the ISR must also have the IRAM_ATTR declared.
252252
Be aware that every function that has this attribute reduces available memory.
253253

254254
In addition, it is not possible to execute delay() or yield() from an ISR,

‎doc/reference.rst

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,13 +9,13 @@ and have several limitations:
99

1010
* Interrupt callback functions must be in IRAM, because the flash may be
1111
in the middle of other operations when they occur. Do this by adding
12-
the ``ICACHE_RAM_ATTR`` attribute on the function definition. If this
12+
the ``IRAM_ATTR`` attribute on the function definition. If this
1313
attribute is not present, the sketch will crash when it attempts to
1414
``attachInterrupt`` with an error message.
1515

1616
.. code:: cpp
1717
18-
ICACHE_RAM_ATTR void gpio_change_handler(void *data) {...
18+
IRAM_ATTR void gpio_change_handler(void *data) {...
1919
2020
* Interrupts must not call ``delay()`` or ``yield()``, or call any routines
2121
which internally use ``delay()`` or ``yield()`` either.
@@ -69,7 +69,7 @@ Pin interrupts are supported through ``attachInterrupt``,
6969
``detachInterrupt`` functions. Interrupts may be attached to any GPIO
7070
pin, except GPIO16. Standard Arduino interrupt types are supported:
7171
``CHANGE``, ``RISING``, ``FALLING``. ISRs need to have
72-
``ICACHE_RAM_ATTR`` before the function definition.
72+
``IRAM_ATTR`` before the function definition.
7373

7474
Analog input
7575
------------

‎libraries/GDBStub/src/internal/gdbstub-cfg.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ likely crash.
6767
#define ATTR_GDBINIT ICACHE_FLASH_ATTR
6868
#endif
6969
#ifndef ATTR_GDBFN
70-
#define ATTR_GDBFN ICACHE_RAM_ATTR
70+
#define ATTR_GDBFN IRAM_ATTR
7171
#endif
7272
#ifndef ATTR_GDBEXTERNFN
7373
#define ATTR_GDBEXTERNFN ICACHE_FLASH_ATTR

‎libraries/SPISlave/src/hspi_slave.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ static void (*_hspi_slave_rx_status_cb)(void * arg, uint32_t data) = NULL;
2828
static void (*_hspi_slave_tx_status_cb)(void * arg) = NULL;
2929
static uint8_t _hspi_slave_buffer[33];
3030

31-
void ICACHE_RAM_ATTR _hspi_slave_isr_handler(void *arg, void *frame)
31+
void IRAM_ATTR _hspi_slave_isr_handler(void *arg, void *frame)
3232
{
3333
(void) frame;
3434
uint32_t status;
@@ -124,7 +124,7 @@ void hspi_slave_end()
124124
SPI1P = B110;
125125
}
126126

127-
void ICACHE_RAM_ATTR hspi_slave_setStatus(uint32_t status)
127+
void IRAM_ATTR hspi_slave_setStatus(uint32_t status)
128128
{
129129
SPI1WS = status;
130130
}

‎tests/device/test_millis_mm/test_millis_mm.ino

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ void view_accsum ( const char *desc, uint16_t *acc, uint16_t *itrm )
109109
//---------------------------------------------------------------------------
110110
// FOR BENCHTEST
111111
// Original millis() function
112-
unsigned long ICACHE_RAM_ATTR millis_orig ( void )
112+
unsigned long IRAM_ATTR millis_orig ( void )
113113
{
114114
// Get usec system time, usec overflow conter
115115
uint32_t m = system_get_time();
@@ -123,7 +123,7 @@ unsigned long ICACHE_RAM_ATTR millis_orig ( void )
123123
// FOR DEBUG
124124
// Corrected millis(), 64-bit arithmetic gold standard
125125
// truncated to 32-bits by return
126-
unsigned long ICACHE_RAM_ATTR millis_corr_DEBUG( void )
126+
unsigned long IRAM_ATTR millis_corr_DEBUG( void )
127127
{
128128
// Get usec system time, usec overflow conter
129129
uint32_t m = system_get_timeA(); // DEBUG
@@ -135,7 +135,7 @@ unsigned long ICACHE_RAM_ATTR millis_corr_DEBUG( void )
135135

136136
//---------------------------------------------------------------------------
137137
// FOR BENCHMARK
138-
unsigned long ICACHE_RAM_ATTR millis_corr ( void )
138+
unsigned long IRAM_ATTR millis_corr ( void )
139139
{
140140
// Get usec system time, usec overflow conter
141141
uint32_t m = system_get_time();
@@ -229,7 +229,7 @@ unsigned long ICACHE_RAM_ATTR millis_corr ( void )
229229
//
230230
// Reference function: corrected millis(), 64-bit arithmetic,
231231
// truncated to 32-bits by return
232-
// unsigned long ICACHE_RAM_ATTR millis_corr_DEBUG( void )
232+
// unsigned long IRAM_ATTR millis_corr_DEBUG( void )
233233
// {
234234
// // Get usec system time, usec overflow conter
235235
// ......
@@ -246,7 +246,7 @@ unsigned long ICACHE_RAM_ATTR millis_corr ( void )
246246
#define MAGIC_1E3_wLO 0x4bc6a7f0 // LS part
247247
#define MAGIC_1E3_wHI 0x00418937 // MS part, magic multiplier
248248

249-
unsigned long ICACHE_RAM_ATTR millis_test_DEBUG ( void )
249+
unsigned long IRAM_ATTR millis_test_DEBUG ( void )
250250
{
251251
union {
252252
uint64_t q; // Accumulator, 64-bit, little endian
@@ -300,7 +300,7 @@ unsigned long ICACHE_RAM_ATTR millis_test_DEBUG ( void )
300300

301301
//---------------------------------------------------------------------------
302302
// FOR BENCHTEST
303-
unsigned long ICACHE_RAM_ATTR millis_test ( void )
303+
unsigned long IRAM_ATTR millis_test ( void )
304304
{
305305
union {
306306
uint64_t q; // Accumulator, 64-bit, little endian

‎tests/host/common/c_types.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -94,16 +94,16 @@ typedef enum {
9494
#define __ICACHE_STRINGIZE_NX(A) #A
9595
#define __ICACHE_STRINGIZE(A) __ICACHE_STRINGIZE_NX(A)
9696
#define ICACHE_FLASH_ATTR __attribute__((section("\".irom0.text." __FILE__ "." __ICACHE_STRINGIZE(__LINE__) "." __ICACHE_STRINGIZE(__COUNTER__) "\"")))
97-
#define ICACHE_RAM_ATTR __attribute__((section("\".iram.text." __FILE__ "." __ICACHE_STRINGIZE(__LINE__) "." __ICACHE_STRINGIZE(__COUNTER__) "\"")))
97+
#define IRAM_ATTR __attribute__((section("\".iram.text." __FILE__ "." __ICACHE_STRINGIZE(__LINE__) "." __ICACHE_STRINGIZE(__COUNTER__) "\"")))
9898
#define ICACHE_RODATA_ATTR __attribute__((section("\".irom.text." __FILE__ "." __ICACHE_STRINGIZE(__LINE__) "." __ICACHE_STRINGIZE(__COUNTER__) "\"")))
9999
#else
100100
#define ICACHE_FLASH_ATTR
101-
#define ICACHE_RAM_ATTR
101+
#define IRAM_ATTR
102102
#define ICACHE_RODATA_ATTR
103103
#endif /* ICACHE_FLASH */
104104

105105
// counterpart https://github.com/espressif/arduino-esp32/blob/master/cores/esp32/esp8266-compat.h
106-
#define IRAM_ATTR ICACHE_RAM_ATTR
106+
#define ICACHE_RAM_ATTR IRAM_ATTR
107107

108108
#define STORE_ATTR __attribute__((aligned(4)))
109109

‎tools/sdk/include/c_types.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -86,15 +86,15 @@ typedef enum {
8686
#ifdef ICACHE_FLASH
8787
#define __ICACHE_STRINGIZE_NX(A) #A
8888
#define __ICACHE_STRINGIZE(A) __ICACHE_STRINGIZE_NX(A)
89-
#define ICACHE_FLASH_ATTR __attribute__((section("\".irom0.text." __FILE__ "." __ICACHE_STRINGIZE(__LINE__) "." __ICACHE_STRINGIZE(__COUNTER__) "\"")))
90-
#define ICACHE_RAM_ATTR __attribute__((section("\".iram.text." __FILE__ "." __ICACHE_STRINGIZE(__LINE__) "." __ICACHE_STRINGIZE(__COUNTER__) "\"")))
89+
#define ICACHE_FLASH_ATTR __attribute__((section("\".irom0.text." __FILE__ "." __ICACHE_STRINGIZE(__LINE__) "." __ICACHE_STRINGIZE(__COUNTER__) "\"")))
90+
#define IRAM_ATTR __attribute__((section("\".iram.text." __FILE__ "." __ICACHE_STRINGIZE(__LINE__) "." __ICACHE_STRINGIZE(__COUNTER__) "\"")))
9191
#else
9292
#define ICACHE_FLASH_ATTR
93-
#define ICACHE_RAM_ATTR
93+
#define IRAM_ATTR
9494
#endif /* ICACHE_FLASH */
9595

9696
// counterpart https://github.com/espressif/arduino-esp32/blob/master/cores/esp32/esp8266-compat.h
97-
#define IRAM_ATTR ICACHE_RAM_ATTR
97+
#define ICACHE_RAM_ATTR IRAM_ATTR __attribute__((deprecated("Use IRAM_ATTR in place of ICACHE_RAM_ATTR to move functions into IRAM")))
9898

9999
#define STORE_ATTR __attribute__((aligned(4)))
100100

‎tools/sizes.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ def get_segment_hints(iram):
2727
hints = {}
2828
hints['ICACHE'] = ' - flash instruction cache'
2929
hints['IROM'] = ' - code in flash (default or ICACHE_FLASH_ATTR)'
30-
hints['IRAM'] = ' / ' + str(iram) + ' - code in IRAM (ICACHE_RAM_ATTR, ISRs...)'
30+
hints['IRAM'] = ' / ' + str(iram) + ' - code in IRAM (IRAM_ATTR, ISRs...)'
3131
hints['DATA'] = ') - initialized variables (global, static) in RAM/HEAP'
3232
hints['RODATA'] = ') / 81920 - constants (global, static) in RAM/HEAP'
3333
hints['BSS'] = ') - zeroed variables (global, static) in RAM/HEAP'

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