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1 parent 08fe7df commit 0f1847cCopy full SHA for 0f1847c
llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -350,7 +350,7 @@ def FeatureStdExtZcd
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[FeatureStdExtZca]>;
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def HasStdExtCOrZcd
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- : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
+ : Predicate<"Subtarget->hasStdExtCOrZcd()">,
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AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
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"'C' (Compressed Instructions) or "
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"'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
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