Skip to content

Commit 533471f

Browse files
atanasyanatanasyan
committedSep 15, 2021
[MIPS] Remove unused tblgen template args. NFC
Identified in D109359.
·
llvmorg-22-initllvmorg-14.0.0-rc1
1 parent 3b9470a commit 533471f

9 files changed

+124
-165
lines changed
 

‎llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -958,7 +958,7 @@ class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct>
958958
let Inst{5-0} = 0b111100;
959959
}
960960

961-
class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst {
961+
class CMP_BRANCH_OFF21_FM_MMR6<bits<6> funct> : MipsR6Inst {
962962
bits<5> rs;
963963
bits<21> offset;
964964

‎llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

Lines changed: 14 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,8 @@ class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
6262
class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
6363
class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
6464
class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
65-
class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>;
66-
class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>;
65+
class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<0b100000>;
66+
class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<0b101000>;
6767
class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>,
6868
DecodeDisambiguates<"POP75GroupBranchMMR6">;
6969
class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
@@ -406,7 +406,7 @@ class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
406406
class BRK_MMR6_DESC : BRK_FT<"break">;
407407

408408
class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
409-
RegisterOperand GPROpnd, InstrItinClass Itin>
409+
InstrItinClass Itin>
410410
: MMR6Arch<instr_asm> {
411411
dag OutOperandList = (outs);
412412
dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
@@ -416,10 +416,8 @@ class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
416416
InstrItinClass Itinerary = Itin;
417417
}
418418

419-
class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd,
420-
II_CACHE>;
421-
class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd,
422-
II_PREF>;
419+
class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, II_CACHE>;
420+
class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, II_PREF>;
423421

424422
class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
425423
RegisterOperand GPROpnd, InstrItinClass Itin>
@@ -1197,21 +1195,21 @@ class SWM16_MMR6_DESC
11971195
ComplexPattern Addr = addr;
11981196
}
11991197

1200-
class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,
1201-
SDPatternOperator OpNode, InstrItinClass Itin,
1202-
Operand MemOpnd>
1198+
class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd,
1199+
InstrItinClass Itin, Operand MemOpnd>
12031200
: MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
12041201
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
12051202
MMR6Arch<opstr> {
12061203
let DecoderMethod = "DecodeMemMMImm4";
12071204
let mayStore = 1;
12081205
}
1209-
class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,
1210-
truncstorei8, II_SB, mem_mm_4>;
1211-
class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
1212-
truncstorei16, II_SH, mem_mm_4_lsl1>;
1213-
class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
1214-
store, II_SW, mem_mm_4_lsl2>;
1206+
1207+
class SB16_MMR6_DESC
1208+
: SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, II_SB, mem_mm_4>;
1209+
class SH16_MMR6_DESC
1210+
: SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, II_SH, mem_mm_4_lsl1>;
1211+
class SW16_MMR6_DESC
1212+
: SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, II_SW, mem_mm_4_lsl2>;
12151213

12161214
class SWSP_MMR6_DESC
12171215
: MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),

‎llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td

Lines changed: 31 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -281,57 +281,46 @@ class SHRLV_PH_MMR2_DESC : SHLLV_R3_MM_DESC_BASE<
281281
class SHRLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE<
282282
"shrlv.qb", int_mips_shrl_qb, NoItinerary, DSPROpnd>;
283283

284-
class EXT_MM_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
285-
InstrItinClass itin> {
284+
class EXT_MM_2R_DESC_BASE<string instr_asm> {
286285
dag OutOperandList = (outs GPR32Opnd:$rt);
287286
dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$rs);
288287
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $rs");
289-
InstrItinClass Itinerary = itin;
288+
InstrItinClass Itinerary = NoItinerary;
290289
}
291-
class EXT_MM_1R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
292-
InstrItinClass itin> {
290+
class EXT_MM_1R_DESC_BASE<string instr_asm> {
293291
dag OutOperandList = (outs GPR32Opnd:$rt);
294292
dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$imm);
295293
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $imm");
296-
InstrItinClass Itinerary = itin;
294+
InstrItinClass Itinerary = NoItinerary;
297295
}
298296

299-
class EXTP_MM_DESC
300-
: EXT_MM_1R_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
301-
Uses<[DSPPos]>, Defs<[DSPEFI]>;
302-
class EXTPDP_MM_DESC
303-
: EXT_MM_1R_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
304-
Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
305-
class EXTPDPV_MM_DESC
306-
: EXT_MM_2R_DESC_BASE<"extpdpv", MipsEXTPDP, NoItinerary>,
307-
Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
308-
class EXTPV_MM_DESC
309-
: EXT_MM_2R_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
310-
Uses<[DSPPos]>, Defs<[DSPEFI]>;
311-
class EXTR_W_MM_DESC
312-
: EXT_MM_1R_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
313-
Defs<[DSPOutFlag23]>;
314-
class EXTR_R_W_MM_DESC
315-
: EXT_MM_1R_DESC_BASE<"extr_r.w", MipsEXTR_R_W, NoItinerary>,
316-
Defs<[DSPOutFlag23]>;
317-
class EXTR_RS_W_MM_DESC
318-
: EXT_MM_1R_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W, NoItinerary>,
319-
Defs<[DSPOutFlag23]>;
320-
class EXTR_S_H_MM_DESC
321-
: EXT_MM_1R_DESC_BASE<"extr_s.h", MipsEXTR_S_H, NoItinerary>,
322-
Defs<[DSPOutFlag23]>;
323-
class EXTRV_W_MM_DESC
324-
: EXT_MM_2R_DESC_BASE<"extrv.w", MipsEXTR_W, NoItinerary>,
325-
Defs<[DSPOutFlag23]>;
326-
class EXTRV_R_W_MM_DESC
327-
: EXT_MM_2R_DESC_BASE<"extrv_r.w", MipsEXTR_R_W, NoItinerary>,
328-
Defs<[DSPOutFlag23]>;
329-
class EXTRV_RS_W_MM_DESC
330-
: EXT_MM_2R_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W, NoItinerary>,
331-
Defs<[DSPOutFlag23]>;
332-
class EXTRV_S_H_MM_DESC
333-
: EXT_MM_2R_DESC_BASE<"extrv_s.h", MipsEXTR_S_H, NoItinerary>,
334-
Defs<[DSPOutFlag23]>;
297+
class EXTP_MM_DESC : EXT_MM_1R_DESC_BASE<"extp">,
298+
Uses<[DSPPos]>,
299+
Defs<[DSPEFI]>;
300+
class EXTPDP_MM_DESC : EXT_MM_1R_DESC_BASE<"extpdp">,
301+
Uses<[DSPPos]>,
302+
Defs<[DSPPos, DSPEFI]>;
303+
class EXTPDPV_MM_DESC : EXT_MM_2R_DESC_BASE<"extpdpv">,
304+
Uses<[DSPPos]>,
305+
Defs<[DSPPos, DSPEFI]>;
306+
class EXTPV_MM_DESC : EXT_MM_2R_DESC_BASE<"extpv">,
307+
Uses<[DSPPos]>,
308+
Defs<[DSPEFI]>;
309+
class EXTR_W_MM_DESC : EXT_MM_1R_DESC_BASE<"extr.w">,
310+
Defs<[DSPOutFlag23]>;
311+
class EXTR_R_W_MM_DESC : EXT_MM_1R_DESC_BASE<"extr_r.w">,
312+
Defs<[DSPOutFlag23]>;
313+
class EXTR_RS_W_MM_DESC : EXT_MM_1R_DESC_BASE<"extr_rs.w">,
314+
Defs<[DSPOutFlag23]>;
315+
class EXTR_S_H_MM_DESC : EXT_MM_1R_DESC_BASE<"extr_s.h">,
316+
Defs<[DSPOutFlag23]>;
317+
class EXTRV_W_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv.w">, Defs<[DSPOutFlag23]>;
318+
class EXTRV_R_W_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv_r.w">,
319+
Defs<[DSPOutFlag23]>;
320+
class EXTRV_RS_W_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv_rs.w">,
321+
Defs<[DSPOutFlag23]>;
322+
class EXTRV_S_H_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv_s.h">,
323+
Defs<[DSPOutFlag23]>;
335324

336325
class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
337326
InstrItinClass itin> {

‎llvm/lib/Target/Mips/MicroMipsInstrInfo.td

Lines changed: 26 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -195,8 +195,7 @@ def simm23_lsl2 : Operand<i32> {
195195
let DecoderMethod = "DecodeSimm23Lsl2";
196196
}
197197

198-
class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
199-
RegisterOperand RO> :
198+
class CompactBranchMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
200199
InstSE<(outs), (ins RO:$rs, opnd:$offset),
201200
!strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
202201
let isBranch = 1;
@@ -240,15 +239,15 @@ MicroMipsInst16<(outs RO1:$rd1, RO2:$rd2), (ins RO3:$rs, RO3:$rt),
240239
let DecoderMethod = "DecodeMovePOperands";
241240
}
242241

243-
class StorePairMM<string opstr, ComplexPattern Addr = addr>
242+
class StorePairMM<string opstr>
244243
: InstSE<(outs), (ins GPR32Opnd:$rt, GPR32Opnd:$rt2, mem_simm12:$addr),
245244
!strconcat(opstr, "\t$rt, $addr"), [], II_SWP, FrmI, opstr> {
246245
let DecoderMethod = "DecodeMemMMImm12";
247246
let mayStore = 1;
248247
let AsmMatchConverter = "ConvertXWPOperands";
249248
}
250249

251-
class LoadPairMM<string opstr, ComplexPattern Addr = addr>
250+
class LoadPairMM<string opstr>
252251
: InstSE<(outs GPR32Opnd:$rt, GPR32Opnd:$rt2), (ins mem_simm12:$addr),
253252
!strconcat(opstr, "\t$rt, $addr"), [], II_LWP, FrmI, opstr> {
254253
let DecoderMethod = "DecodeMemMMImm12";
@@ -332,7 +331,7 @@ class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
332331
MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
333332
!strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
334333

335-
class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
334+
class LoadMM16<string opstr, DAGOperand RO,
336335
InstrItinClass Itin, Operand MemOpnd> :
337336
MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
338337
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
@@ -341,8 +340,7 @@ class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
341340
let mayLoad = 1;
342341
}
343342

344-
class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
345-
SDPatternOperator OpNode, InstrItinClass Itin,
343+
class StoreMM16<string opstr, DAGOperand RTOpnd, InstrItinClass Itin,
346344
Operand MemOpnd> :
347345
MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
348346
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
@@ -499,8 +497,7 @@ let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
499497
!strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;
500498
}
501499

502-
class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
503-
SDPatternOperator OpNode = null_frag> :
500+
class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO> :
504501
InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
505502
!strconcat(opstr, "\t$rd, ${index}(${base})"), [], II_LWXS, FrmFI>;
506503

@@ -540,34 +537,28 @@ def reglist16 : Operand<i32> {
540537
let ParserMatchClass = RegList16AsmOperand;
541538
}
542539

543-
class StoreMultMM<string opstr,
544-
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
540+
class StoreMultMM<string opstr, InstrItinClass Itin> :
545541
InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
546542
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
547543
let DecoderMethod = "DecodeMemMMImm12";
548544
let mayStore = 1;
549545
}
550546

551-
class LoadMultMM<string opstr,
552-
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
547+
class LoadMultMM<string opstr, InstrItinClass Itin> :
553548
InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
554549
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
555550
let DecoderMethod = "DecodeMemMMImm12";
556551
let mayLoad = 1;
557552
}
558553

559-
class StoreMultMM16<string opstr,
560-
InstrItinClass Itin = NoItinerary,
561-
ComplexPattern Addr = addr> :
554+
class StoreMultMM16<string opstr, InstrItinClass Itin> :
562555
MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
563556
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
564557
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
565558
let mayStore = 1;
566559
}
567560

568-
class LoadMultMM16<string opstr,
569-
InstrItinClass Itin = NoItinerary,
570-
ComplexPattern Addr = addr> :
561+
class LoadMultMM16<string opstr, InstrItinClass Itin> :
571562
MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
572563
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
573564
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
@@ -636,21 +627,21 @@ let FastISelShouldIgnore = 1 in {
636627
def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
637628
LOGIC_FM_MM16<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;
638629
}
639-
def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
640-
mem_mm_4>, LOAD_STORE_FM_MM16<0x02>, ISA_MICROMIPS;
641-
def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
642-
mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>, ISA_MICROMIPS;
643-
def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
630+
def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, II_LBU, mem_mm_4>,
631+
LOAD_STORE_FM_MM16<0x02>, ISA_MICROMIPS;
632+
def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, II_LHU, mem_mm_4_lsl1>,
633+
LOAD_STORE_FM_MM16<0x0a>, ISA_MICROMIPS;
634+
def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, II_LW, mem_mm_4_lsl2>,
644635
LOAD_STORE_FM_MM16<0x1a>, ISA_MICROMIPS;
645-
def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
646-
II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>,
647-
ISA_MICROMIPS32_NOT_MIPS32R6;
648-
def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
649-
II_SH, mem_mm_4_lsl1>,
650-
LOAD_STORE_FM_MM16<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6;
651-
def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
652-
mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>,
653-
ISA_MICROMIPS32_NOT_MIPS32R6;
636+
def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, II_SB, mem_mm_4>,
637+
LOAD_STORE_FM_MM16<0x22>,
638+
ISA_MICROMIPS32_NOT_MIPS32R6;
639+
def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, II_SH, mem_mm_4_lsl1>,
640+
LOAD_STORE_FM_MM16<0x2a>,
641+
ISA_MICROMIPS32_NOT_MIPS32R6;
642+
def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, II_SW, mem_mm_4_lsl2>,
643+
LOAD_STORE_FM_MM16<0x3a>,
644+
ISA_MICROMIPS32_NOT_MIPS32R6;
654645
def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_simm7_lsl2>,
655646
LOAD_GP_FM_MM16<0x19>, ISA_MICROMIPS;
656647
def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
@@ -713,9 +704,9 @@ let DecoderNamespace = "MicroMips" in {
713704
POOL32A_CFTC2_FM_MM<0b1101110100>, ISA_MICROMIPS;
714705

715706
/// Compact Branch Instructions
716-
def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
707+
def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, GPR32Opnd>,
717708
COMPACT_BRANCH_FM_MM<0x7>, ISA_MICROMIPS32_NOT_MIPS32R6;
718-
def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
709+
def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, GPR32Opnd>,
719710
COMPACT_BRANCH_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;
720711

721712
/// Arithmetic Instructions (ALU Immediate)

‎llvm/lib/Target/Mips/Mips16InstrInfo.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -304,14 +304,14 @@ class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
304304
//
305305
// MULT
306306
//
307-
class FMULT16_ins<string asmstr, InstrItinClass itin> :
307+
class FMULT16_ins<string asmstr> :
308308
MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
309309
!strconcat(asmstr, "\t$rx, $ry"), []>;
310310

311311
//
312312
// MULT-LO
313313
//
314-
class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
314+
class FMULT16_LO_ins<string asmstr> :
315315
MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
316316
!strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
317317
let isCodeGenOnly=1;
@@ -895,13 +895,13 @@ def Mflo16: FRR16_M_ins<0b10010, "mflo", IIM16Alu> {
895895
//
896896
// Pseudo Instruction for mult
897897
//
898-
def MultRxRy16: FMULT16_ins<"mult", IIM16Alu> {
898+
def MultRxRy16: FMULT16_ins<"mult"> {
899899
let isCommutable = 1;
900900
let hasSideEffects = 0;
901901
let Defs = [HI0, LO0];
902902
}
903903

904-
def MultuRxRy16: FMULT16_ins<"multu", IIM16Alu> {
904+
def MultuRxRy16: FMULT16_ins<"multu"> {
905905
let isCommutable = 1;
906906
let hasSideEffects = 0;
907907
let Defs = [HI0, LO0];
@@ -912,7 +912,7 @@ def MultuRxRy16: FMULT16_ins<"multu", IIM16Alu> {
912912
// Purpose: Multiply Word
913913
// To multiply 32-bit signed integers.
914914
//
915-
def MultRxRyRz16: FMULT16_LO_ins<"mult", IIM16Alu> {
915+
def MultRxRyRz16: FMULT16_LO_ins<"mult"> {
916916
let isCommutable = 1;
917917
let hasSideEffects = 0;
918918
let Defs = [HI0, LO0];
@@ -923,7 +923,7 @@ def MultRxRyRz16: FMULT16_LO_ins<"mult", IIM16Alu> {
923923
// Purpose: Multiply Unsigned Word
924924
// To multiply 32-bit unsigned integers.
925925
//
926-
def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIM16Alu> {
926+
def MultuRxRyRz16: FMULT16_LO_ins<"multu"> {
927927
let isCommutable = 1;
928928
let hasSideEffects = 0;
929929
let Defs = [HI0, LO0];

‎llvm/lib/Target/Mips/Mips32r6InstrInfo.td

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -700,8 +700,7 @@ class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd, II_RINT_D>;
700700
class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd, II_CLASS_S>;
701701
class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd, II_CLASS_D>;
702702

703-
class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd,
704-
RegisterOperand GPROpnd, InstrItinClass itin>
703+
class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd, InstrItinClass itin>
705704
: MipsR6Arch<instr_asm> {
706705
dag OutOperandList = (outs);
707706
dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
@@ -711,8 +710,8 @@ class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd,
711710
InstrItinClass Itinerary = itin;
712711
}
713712

714-
class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd, II_CACHE>;
715-
class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd, II_PREF>;
713+
class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, II_CACHE>;
714+
class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, II_PREF>;
716715

717716
class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,
718717
InstrItinClass itin> {

‎llvm/lib/Target/Mips/MipsDSPInstrInfo.td

Lines changed: 18 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -398,17 +398,15 @@ class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
398398
string BaseOpcode = instr_asm;
399399
}
400400

401-
class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
402-
InstrItinClass itin> {
401+
class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, InstrItinClass itin> {
403402
dag OutOperandList = (outs GPR32Opnd:$rt);
404403
dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
405404
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
406405
InstrItinClass Itinerary = itin;
407406
string BaseOpcode = instr_asm;
408407
}
409408

410-
class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
411-
InstrItinClass itin> {
409+
class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, InstrItinClass itin> {
412410
dag OutOperandList = (outs GPR32Opnd:$rt);
413411
dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$shift_rs);
414412
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
@@ -522,7 +520,7 @@ class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO,
522520
bit isMoveReg = 1;
523521
}
524522

525-
class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
523+
class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode> :
526524
MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
527525
bit hasNoSchedulingInfo = 1;
528526
bit usesCustomInserter = 1;
@@ -891,47 +889,40 @@ class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
891889
class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;
892890

893891
// Extr
894-
class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
892+
class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", NoItinerary>,
895893
Uses<[DSPPos]>, Defs<[DSPEFI]>;
896894

897-
class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
895+
class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", NoItinerary>,
898896
Uses<[DSPPos]>, Defs<[DSPEFI]>;
899897

900-
class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
898+
class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", NoItinerary>,
901899
Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
902900

903-
class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
904-
NoItinerary>,
901+
class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", NoItinerary>,
905902
Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
906903

907-
class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
904+
class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", NoItinerary>,
908905
Defs<[DSPOutFlag23]>;
909906

910-
class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
911-
NoItinerary>, Defs<[DSPOutFlag23]>;
907+
class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", NoItinerary>,
908+
Defs<[DSPOutFlag23]>;
912909

913-
class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
914-
NoItinerary>,
910+
class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", NoItinerary>,
915911
Defs<[DSPOutFlag23]>;
916912

917-
class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
918-
NoItinerary>,
913+
class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", NoItinerary>,
919914
Defs<[DSPOutFlag23]>;
920915

921-
class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
922-
NoItinerary>,
916+
class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", NoItinerary>,
923917
Defs<[DSPOutFlag23]>;
924918

925-
class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
926-
NoItinerary>,
919+
class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", NoItinerary>,
927920
Defs<[DSPOutFlag23]>;
928921

929-
class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
930-
NoItinerary>,
922+
class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", NoItinerary>,
931923
Defs<[DSPOutFlag23]>;
932924

933-
class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
934-
NoItinerary>,
925+
class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", NoItinerary>,
935926
Defs<[DSPOutFlag23]>;
936927

937928
class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
@@ -1115,8 +1106,8 @@ class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,
11151106
timmZExt5, NoItinerary>;
11161107

11171108
// Pseudos.
1118-
def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1119-
NoItinerary>, Uses<[DSPPos]>;
1109+
def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32>,
1110+
Uses<[DSPPos]>;
11201111

11211112
// Instruction defs.
11221113
// MIPS DSP Rev 1

‎llvm/lib/Target/Mips/MipsEVAInstrInfo.td

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -70,8 +70,7 @@ class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd, II_LHUE>;
7070
class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd, II_LWE>;
7171

7272
class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
73-
SDPatternOperator OpNode = null_frag,
74-
InstrItinClass itin = NoItinerary> {
73+
InstrItinClass itin> {
7574
dag OutOperandList = (outs);
7675
dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
7776
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
@@ -82,9 +81,9 @@ class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
8281
InstrItinClass Itinerary = itin;
8382
}
8483

85-
class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd, null_frag, II_SBE>;
86-
class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd, null_frag, II_SHE>;
87-
class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd, null_frag, II_SWE>;
84+
class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd, II_SBE>;
85+
class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd, II_SHE>;
86+
class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd, II_SWE>;
8887

8988
// Load/Store Left/Right EVA descriptions
9089
class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,

‎llvm/lib/Target/Mips/MipsMSAInstrInfo.td

Lines changed: 21 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1308,8 +1308,8 @@ class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
13081308
InstrItinClass Itinerary = itin;
13091309
}
13101310

1311-
class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1312-
RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1311+
class MSA_2R_FILL_PSEUDO_BASE<SDPatternOperator OpNode,
1312+
RegisterClass RCWD, RegisterClass RCWS> :
13131313
MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
13141314
[(set RCWD:$wd, (OpNode RCWS:$fs))]> {
13151315
let usesCustomInserter = 1;
@@ -2091,10 +2091,8 @@ class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
20912091
class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64,
20922092
MSA128DOpnd, GPR64Opnd>;
20932093

2094-
class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
2095-
FGR32>;
2096-
class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
2097-
FGR64>;
2094+
class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<vsplatf32, MSA128W, FGR32>;
2095+
class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<vsplatf64, MSA128D, FGR64>;
20982096

20992097
class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
21002098
class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
@@ -3755,36 +3753,30 @@ def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
37553753
// Pseudos used to implement BNZ.df, and BZ.df
37563754

37573755
class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3758-
RegisterClass RCWS,
3759-
InstrItinClass itin = NoItinerary> :
3756+
RegisterClass RCWS> :
37603757
MipsPseudo<(outs GPR32:$dst),
37613758
(ins RCWS:$ws),
37623759
[(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
37633760
bit usesCustomInserter = 1;
37643761
bit hasNoSchedulingInfo = 1;
37653762
}
37663763

3767-
def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3768-
MSA128B, NoItinerary>;
3769-
def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3770-
MSA128H, NoItinerary>;
3771-
def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3772-
MSA128W, NoItinerary>;
3773-
def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3774-
MSA128D, NoItinerary>;
3775-
def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3776-
MSA128B, NoItinerary>;
3777-
3778-
def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3779-
MSA128B, NoItinerary>;
3780-
def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3781-
MSA128H, NoItinerary>;
3782-
def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3783-
MSA128W, NoItinerary>;
3784-
def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3785-
MSA128D, NoItinerary>;
3786-
def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3787-
MSA128B, NoItinerary>;
3764+
def SNZ_B_PSEUDO
3765+
: MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, MSA128B>;
3766+
def SNZ_H_PSEUDO
3767+
: MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, MSA128H>;
3768+
def SNZ_W_PSEUDO
3769+
: MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, MSA128W>;
3770+
def SNZ_D_PSEUDO
3771+
: MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, MSA128D>;
3772+
def SNZ_V_PSEUDO
3773+
: MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, MSA128B>;
3774+
3775+
def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, MSA128B>;
3776+
def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, MSA128H>;
3777+
def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, MSA128W>;
3778+
def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, MSA128D>;
3779+
def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, MSA128B>;
37883780

37893781
// Pseudoes used to implement transparent fp16 support.
37903782

0 commit comments

Comments
 (0)
Please sign in to comment.