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[X86] Add some initial test coverage for half libcall expansion/promotion
We can add additional tests in the future, but this is an initial placeholder Inspired by #105775
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‎llvm/test/CodeGen/X86/fp16-libcalls.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -enable-legalize-types-checking -mtriple=x86_64-linux-gnu -mattr=+f16c | FileCheck %s --check-prefix=F16C
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; RUN: llc < %s -enable-legalize-types-checking -mtriple=x86_64-linux-gnu -mattr=+avx512fp16 | FileCheck %s --check-prefix=FP16
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; RUN: llc < %s -enable-legalize-types-checking -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -enable-legalize-types-checking -mtriple=i686-linux-gnu -mattr=sse2 | FileCheck %s --check-prefix=X86
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; Check all soft floating point library function calls.
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define void @test_half_ceil(half %a0, ptr %p0) nounwind {
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; F16C-LABEL: test_half_ceil:
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; F16C: # %bb.0:
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; F16C-NEXT: vpextrw $0, %xmm0, %eax
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; F16C-NEXT: vmovd %eax, %xmm0
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; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
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; F16C-NEXT: vroundss $10, %xmm0, %xmm0, %xmm0
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; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
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; F16C-NEXT: vmovd %xmm0, %eax
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; F16C-NEXT: movw %ax, (%rdi)
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; F16C-NEXT: retq
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;
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; FP16-LABEL: test_half_ceil:
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; FP16: # %bb.0:
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; FP16-NEXT: vrndscalesh $10, %xmm0, %xmm0, %xmm0
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; FP16-NEXT: vmovsh %xmm0, (%rdi)
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; FP16-NEXT: retq
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;
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; X64-LABEL: test_half_ceil:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rbx
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; X64-NEXT: movq %rdi, %rbx
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; X64-NEXT: callq __extendhfsf2@PLT
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; X64-NEXT: callq ceilf@PLT
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; X64-NEXT: callq __truncsfhf2@PLT
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; X64-NEXT: pextrw $0, %xmm0, %eax
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; X64-NEXT: movw %ax, (%rbx)
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; X64-NEXT: popq %rbx
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; X64-NEXT: retq
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;
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; X86-LABEL: test_half_ceil:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esp)
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; X86-NEXT: calll __extendhfsf2
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; X86-NEXT: fstps (%esp)
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; X86-NEXT: calll ceilf
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; X86-NEXT: fstps (%esp)
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; X86-NEXT: calll __truncsfhf2
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esi)
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; X86-NEXT: addl $8, %esp
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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%res = call half @llvm.ceil.half(half %a0)
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store half %res, ptr %p0, align 2
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ret void
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}
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define void @test_half_cos(half %a0, ptr %p0) nounwind {
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; F16C-LABEL: test_half_cos:
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; F16C: # %bb.0:
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; F16C-NEXT: pushq %rbx
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; F16C-NEXT: movq %rdi, %rbx
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; F16C-NEXT: vpextrw $0, %xmm0, %eax
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; F16C-NEXT: vmovd %eax, %xmm0
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; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
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; F16C-NEXT: callq cosf@PLT
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; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
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; F16C-NEXT: vmovd %xmm0, %eax
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; F16C-NEXT: movw %ax, (%rbx)
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; F16C-NEXT: popq %rbx
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; F16C-NEXT: retq
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;
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; FP16-LABEL: test_half_cos:
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; FP16: # %bb.0:
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; FP16-NEXT: pushq %rbx
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; FP16-NEXT: movq %rdi, %rbx
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; FP16-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
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; FP16-NEXT: callq cosf@PLT
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; FP16-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
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; FP16-NEXT: vmovsh %xmm0, (%rbx)
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; FP16-NEXT: popq %rbx
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; FP16-NEXT: retq
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;
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; X64-LABEL: test_half_cos:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rbx
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; X64-NEXT: movq %rdi, %rbx
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; X64-NEXT: callq __extendhfsf2@PLT
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; X64-NEXT: callq cosf@PLT
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; X64-NEXT: callq __truncsfhf2@PLT
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; X64-NEXT: pextrw $0, %xmm0, %eax
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; X64-NEXT: movw %ax, (%rbx)
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; X64-NEXT: popq %rbx
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; X64-NEXT: retq
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;
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; X86-LABEL: test_half_cos:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esp)
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; X86-NEXT: calll __extendhfsf2
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; X86-NEXT: fstps (%esp)
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; X86-NEXT: calll cosf
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; X86-NEXT: fstps (%esp)
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; X86-NEXT: calll __truncsfhf2
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esi)
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; X86-NEXT: addl $8, %esp
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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%res = call half @llvm.cos.half(half %a0)
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store half %res, ptr %p0, align 2
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ret void
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}
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define void @test_half_fabs(half %a0, ptr %p0) nounwind {
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; F16C-LABEL: test_half_fabs:
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; F16C: # %bb.0:
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; F16C-NEXT: vpextrw $0, %xmm0, %eax
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; F16C-NEXT: vmovd %eax, %xmm0
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; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
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; F16C-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
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; F16C-NEXT: vmovd %xmm0, %eax
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; F16C-NEXT: movw %ax, (%rdi)
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; F16C-NEXT: retq
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;
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; FP16-LABEL: test_half_fabs:
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; FP16: # %bb.0:
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; FP16-NEXT: vpbroadcastw {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
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; FP16-NEXT: vpand %xmm1, %xmm0, %xmm0
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; FP16-NEXT: vmovsh %xmm0, (%rdi)
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; FP16-NEXT: retq
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;
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; X64-LABEL: test_half_fabs:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rbx
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; X64-NEXT: movq %rdi, %rbx
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; X64-NEXT: callq __extendhfsf2@PLT
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; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; X64-NEXT: callq __truncsfhf2@PLT
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; X64-NEXT: pextrw $0, %xmm0, %eax
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; X64-NEXT: movw %ax, (%rbx)
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; X64-NEXT: popq %rbx
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; X64-NEXT: retq
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;
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; X86-LABEL: test_half_fabs:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esp)
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; X86-NEXT: calll __extendhfsf2
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; X86-NEXT: fstps {{[0-9]+}}(%esp)
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; X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
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; X86-NEXT: movd %xmm0, (%esp)
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; X86-NEXT: calll __truncsfhf2
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esi)
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; X86-NEXT: addl $8, %esp
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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%res = call half @llvm.fabs.half(half %a0)
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store half %res, ptr %p0, align 2
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ret void
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}
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define void @test_half_pow(half %a0, half %a1, ptr %p0) nounwind {
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; F16C-LABEL: test_half_pow:
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; F16C: # %bb.0:
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; F16C-NEXT: pushq %rbx
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; F16C-NEXT: movq %rdi, %rbx
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; F16C-NEXT: vpextrw $0, %xmm1, %eax
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; F16C-NEXT: vpextrw $0, %xmm0, %ecx
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; F16C-NEXT: vmovd %ecx, %xmm0
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; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
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; F16C-NEXT: vmovd %eax, %xmm1
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; F16C-NEXT: vcvtph2ps %xmm1, %xmm1
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; F16C-NEXT: callq powf@PLT
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; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
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; F16C-NEXT: vmovd %xmm0, %eax
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; F16C-NEXT: movw %ax, (%rbx)
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; F16C-NEXT: popq %rbx
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; F16C-NEXT: retq
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;
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; FP16-LABEL: test_half_pow:
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; FP16: # %bb.0:
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; FP16-NEXT: pushq %rbx
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; FP16-NEXT: movq %rdi, %rbx
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; FP16-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
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; FP16-NEXT: vcvtsh2ss %xmm1, %xmm1, %xmm1
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; FP16-NEXT: callq powf@PLT
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; FP16-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
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; FP16-NEXT: vmovsh %xmm0, (%rbx)
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; FP16-NEXT: popq %rbx
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; FP16-NEXT: retq
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;
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; X64-LABEL: test_half_pow:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rbx
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; X64-NEXT: subq $16, %rsp
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; X64-NEXT: movq %rdi, %rbx
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; X64-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; X64-NEXT: movaps %xmm1, %xmm0
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; X64-NEXT: callq __extendhfsf2@PLT
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; X64-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
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; X64-NEXT: movd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Folded Reload
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; X64-NEXT: # xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: callq __extendhfsf2@PLT
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; X64-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
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; X64-NEXT: # xmm1 = mem[0],zero,zero,zero
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; X64-NEXT: callq powf@PLT
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; X64-NEXT: callq __truncsfhf2@PLT
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; X64-NEXT: pextrw $0, %xmm0, %eax
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; X64-NEXT: movw %ax, (%rbx)
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; X64-NEXT: addq $16, %rsp
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; X64-NEXT: popq %rbx
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; X64-NEXT: retq
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;
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; X86-LABEL: test_half_pow:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: subl $56, %esp
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; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
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; X86-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
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; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esp)
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; X86-NEXT: calll __extendhfsf2
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; X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
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; X86-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esp)
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; X86-NEXT: calll __extendhfsf2
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; X86-NEXT: fstps {{[0-9]+}}(%esp)
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; X86-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
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; X86-NEXT: fstps (%esp)
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; X86-NEXT: calll powf
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; X86-NEXT: fstps (%esp)
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; X86-NEXT: calll __truncsfhf2
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esi)
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; X86-NEXT: addl $56, %esp
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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%res = call half @llvm.pow.half(half %a0, half %a1)
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store half %res, ptr %p0, align 2
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ret void
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}
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define void @test_half_sin(half %a0, ptr %p0) nounwind {
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; F16C-LABEL: test_half_sin:
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; F16C: # %bb.0:
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; F16C-NEXT: pushq %rbx
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; F16C-NEXT: movq %rdi, %rbx
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; F16C-NEXT: vpextrw $0, %xmm0, %eax
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; F16C-NEXT: vmovd %eax, %xmm0
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; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
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; F16C-NEXT: callq sinf@PLT
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; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
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; F16C-NEXT: vmovd %xmm0, %eax
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; F16C-NEXT: movw %ax, (%rbx)
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; F16C-NEXT: popq %rbx
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; F16C-NEXT: retq
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;
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; FP16-LABEL: test_half_sin:
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; FP16: # %bb.0:
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; FP16-NEXT: pushq %rbx
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; FP16-NEXT: movq %rdi, %rbx
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; FP16-NEXT: vcvtsh2ss %xmm0, %xmm0, %xmm0
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; FP16-NEXT: callq sinf@PLT
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; FP16-NEXT: vcvtss2sh %xmm0, %xmm0, %xmm0
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; FP16-NEXT: vmovsh %xmm0, (%rbx)
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; FP16-NEXT: popq %rbx
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; FP16-NEXT: retq
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;
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; X64-LABEL: test_half_sin:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rbx
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; X64-NEXT: movq %rdi, %rbx
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; X64-NEXT: callq __extendhfsf2@PLT
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; X64-NEXT: callq sinf@PLT
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; X64-NEXT: callq __truncsfhf2@PLT
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; X64-NEXT: pextrw $0, %xmm0, %eax
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; X64-NEXT: movw %ax, (%rbx)
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; X64-NEXT: popq %rbx
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; X64-NEXT: retq
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;
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; X86-LABEL: test_half_sin:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esp)
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; X86-NEXT: calll __extendhfsf2
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; X86-NEXT: fstps (%esp)
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; X86-NEXT: calll sinf
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; X86-NEXT: fstps (%esp)
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; X86-NEXT: calll __truncsfhf2
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esi)
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; X86-NEXT: addl $8, %esp
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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%res = call half @llvm.sin.half(half %a0)
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store half %res, ptr %p0, align 2
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ret void
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}
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define void @test_half_sqrt(half %a0, ptr %p0) nounwind {
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; F16C-LABEL: test_half_sqrt:
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; F16C: # %bb.0:
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; F16C-NEXT: vpextrw $0, %xmm0, %eax
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; F16C-NEXT: vmovd %eax, %xmm0
328+
; F16C-NEXT: vcvtph2ps %xmm0, %xmm0
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; F16C-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
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; F16C-NEXT: vmovd %xmm0, %eax
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; F16C-NEXT: movw %ax, (%rdi)
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; F16C-NEXT: retq
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;
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; FP16-LABEL: test_half_sqrt:
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; FP16: # %bb.0:
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; FP16-NEXT: vsqrtsh %xmm0, %xmm0, %xmm0
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; FP16-NEXT: vmovsh %xmm0, (%rdi)
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; FP16-NEXT: retq
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;
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; X64-LABEL: test_half_sqrt:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rbx
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; X64-NEXT: movq %rdi, %rbx
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; X64-NEXT: callq __extendhfsf2@PLT
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; X64-NEXT: sqrtss %xmm0, %xmm0
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; X64-NEXT: callq __truncsfhf2@PLT
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; X64-NEXT: pextrw $0, %xmm0, %eax
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; X64-NEXT: movw %ax, (%rbx)
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; X64-NEXT: popq %rbx
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; X64-NEXT: retq
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;
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; X86-LABEL: test_half_sqrt:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
356+
; X86-NEXT: subl $8, %esp
357+
; X86-NEXT: pinsrw $0, {{[0-9]+}}(%esp), %xmm0
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esp)
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; X86-NEXT: calll __extendhfsf2
362+
; X86-NEXT: fstps {{[0-9]+}}(%esp)
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; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-NEXT: sqrtss %xmm0, %xmm0
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; X86-NEXT: movss %xmm0, (%esp)
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; X86-NEXT: calll __truncsfhf2
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; X86-NEXT: pextrw $0, %xmm0, %eax
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; X86-NEXT: movw %ax, (%esi)
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; X86-NEXT: addl $8, %esp
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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%res = call half @llvm.sqrt.half(half %a0)
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store half %res, ptr %p0, align 2
374+
ret void
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}

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