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Merge remote-tracking branch 'refs/remotes/remote/master'
2 parents 9ea38b3 + 45f1ce7 commit 393fa76

8 files changed

Lines changed: 239 additions & 166 deletions

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AltairZ80/s100_icom.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1434,8 +1434,6 @@ static uint8 ICOM_Command(UNIT *uptr, ICOM_REG *pICOM, int32 Data)
14341434
pICOM->status &= ~ICOM_STAT_DRVFAIL;
14351435
pICOM->status &= ~ICOM_STAT_CRC;
14361436
pICOM->status &= ~ICOM_STAT_DDM;
1437-
pICOM->rDataBuf = 0;
1438-
pICOM->wDataBuf = 0;
14391437
break;
14401438

14411439
case ICOM_CMD_LDCONF:

PDP10/kx10_cpu.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -781,7 +781,7 @@ DEVICE cpu_dev = {
781781
#if PIDP10
782782
/* Update MI register if address matches */
783783
#define UPDATE_MI(a) if (!MI_flag && a == AS) { \
784-
MI = MB; \
784+
MI = MB; \
785785
}
786786
#else
787787
#define UPDATE_MI(a)
@@ -2331,7 +2331,7 @@ int Mem_write(int flag, int cur_context) {
23312331
if (sim_brk_summ && sim_brk_test(last_addr, SWMASK('W')))
23322332
watch_stop = 1;
23332333
M[last_addr] = MB;
2334-
UPDATE_MI(last_addr);
2334+
UPDATE_MI(last_addr);
23352335
modify = 0;
23362336
return 0;
23372337
}

PDP11/pdp11_rr.c

Lines changed: 134 additions & 118 deletions
Large diffs are not rendered by default.

PDP18B/pdp18b_dpy.c

Lines changed: 77 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
/* pdp18b_dpy.c: PDP-7 Type 340 interface
1+
/* pdp18b_dpy.c: PDP-7 Type 34 and Type 340 interface
22
3-
Copyright (c) 2019, Lars Brinkhoff
3+
Copyright (c) 2019, 2026, Lars Brinkhoff
44
55
Permission is hereby granted, free of charge, to any person obtaining a
66
copy of this software and associated documentation files (the "Software"),
@@ -38,6 +38,11 @@
3838
#define DBG_IOT 001 /* IOT instructions. */
3939
#define DBG_IRQ 002 /* Interrupts. */
4040
#define DBG_INS 004 /* 340 instructions. */
41+
#define DBG_PLT 010 /* Points plotted. */
42+
43+
#define UNIT_V_TYPE34 (UNIT_V_UF + 0) /* Type 34 */
44+
#define UNIT_TYPE34 (1 << UNIT_V_TYPE34)
45+
#define TYPE34 (dpy_unit[0].flags & UNIT_TYPE34)
4146

4247
/*
4348
* Number of microseconds between svc calls. Used to age display and
@@ -63,23 +68,33 @@ DEBTAB dpy_deb[] = {
6368
{ "IOT", DBG_IOT },
6469
{ "IRQ", DBG_IRQ },
6570
{ "INS", DBG_INS },
71+
{ "PLT", DBG_PLT },
6672
{ NULL, 0 }
6773
};
6874

75+
MTAB dpy_mod[] = {
76+
{ UNIT_TYPE34, UNIT_TYPE34, "Type 34", "TYPE34", NULL },
77+
{ UNIT_TYPE34, 0, "Type 340", "TYPE340", NULL },
78+
{ 0 }
79+
};
80+
6981
DEVICE dpy_dev = {
70-
"DPY", dpy_unit, NULL, NULL,
82+
"DPY", dpy_unit, NULL, dpy_mod,
7183
1, 8, 12, 1, 8, 18,
7284
NULL, NULL, &dpy_reset,
7385
NULL, NULL, NULL,
7486
&dpy_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG, 0,
7587
dpy_deb, NULL, NULL
7688
};
7789

90+
static uint16 dpy_x, dpy_y, dpy_i;
91+
7892
t_stat dpy_svc (UNIT *uptr)
7993
{
8094
sim_activate_after(uptr, DPY_CYCLE_US);
8195
display_age(DPY_CYCLE_US, 0);
82-
ty340_cycle();
96+
if (!TYPE34)
97+
ty340_cycle();
8398
return SCPE_OK;
8499
}
85100

@@ -95,7 +110,10 @@ t_stat dpy_reset (DEVICE *dptr)
95110
display_reset();
96111
ty340_reset(dptr);
97112
}
98-
sim_cancel (&dpy_unit[0]);
113+
if (TYPE34)
114+
sim_activate_abs (dpy_unit, 0);
115+
else
116+
sim_cancel (&dpy_unit[0]);
99117
return SCPE_OK;
100118
}
101119

@@ -132,18 +150,34 @@ int32 dpy05 (int32 dev, int32 pulse, int32 dat)
132150
{
133151
sim_debug(DBG_IOT, &dpy_dev, "7005%02o, %06o\n", pulse, dat);
134152

135-
if (pulse & 001) {
153+
if ((pulse & 001) != 0 && !TYPE34) {
136154
if (ty340_sense(ST340_VEDGE))
137155
dat |= IOT_SKP;
138156
}
139157

140158
if (pulse & 002) {
141-
dat |= ty340_get_dac();
159+
if (TYPE34) {
160+
sim_debug(DBG_IOT, &dpy_dev, "Clear X\n");
161+
dpy_x = 0;
162+
} else {
163+
dat |= ty340_get_dac();
164+
}
142165
}
143166

144167
if (pulse & 004) {
145-
ty340_clear (ST340_LPHIT);
146-
sim_activate_abs (dpy_unit, 0);
168+
if (TYPE34) {
169+
dpy_x |= dat & 01777;
170+
sim_debug(DBG_IOT, &dpy_dev, "Set X to %04o\n", dpy_x);
171+
} else {
172+
ty340_clear (ST340_LPHIT);
173+
sim_activate_abs (dpy_unit, 0);
174+
}
175+
}
176+
177+
if ((pulse & 040) != 0 && TYPE34) {
178+
sim_debug(DBG_PLT, &dpy_dev, "Plot %04o,%04o intensity %o\n",
179+
dpy_x, dpy_y, dpy_i);
180+
display_point (dpy_x, dpy_y, (dpy_i * DISPLAY_INT_MAX) / 7, 0);
147181
}
148182

149183
return dat;
@@ -153,20 +187,36 @@ int32 dpy06 (int32 dev, int32 pulse, int32 dat)
153187
{
154188
sim_debug(DBG_IOT, &dpy_dev, "7006%02o, %06o\n", pulse, dat);
155189

156-
if (pulse & 001) {
190+
if ((pulse & 001) != 0 && !TYPE34) {
157191
if (ty340_sense(ST340_STOPPED))
158192
dat |= IOT_SKP;
159193
}
160194

161195
if (pulse & 002) {
162-
ty340_set_dac (0);
196+
if (TYPE34) {
197+
sim_debug(DBG_IOT, &dpy_dev, "Clear Y\n");
198+
dpy_y = 0;
199+
} else {
200+
ty340_set_dac (0);
201+
}
163202
}
164203

165204
if (pulse & 004) {
166-
if ((pulse & 010) == 0)
167-
ty340_set_dac (dat & 07777);
168-
ty340_clear (ST340_STOPPED|ST340_STOP_INT);
169-
sim_activate_abs (dpy_unit, 0);
205+
if (TYPE34) {
206+
dpy_y |= dat & 01777;
207+
sim_debug(DBG_IOT, &dpy_dev, "Set Y to %04o\n", dpy_y);
208+
} else {
209+
if ((pulse & 010) == 0)
210+
ty340_set_dac (dat & 07777);
211+
ty340_clear (ST340_STOPPED|ST340_STOP_INT);
212+
sim_activate_abs (dpy_unit, 0);
213+
}
214+
}
215+
216+
if ((pulse & 040) != 0 && TYPE34) {
217+
sim_debug(DBG_PLT, &dpy_dev, "Plot %04o,%04o intensity %o\n",
218+
dpy_x, dpy_y, dpy_i);
219+
display_point (dpy_x, dpy_y, (dpy_i * DISPLAY_INT_MAX) / 7, 0);
170220
}
171221

172222
return dat;
@@ -176,6 +226,15 @@ int32 dpy07 (int32 dev, int32 pulse, int32 dat)
176226
{
177227
sim_debug(DBG_IOT, &dpy_dev, "7007%02o, %06o\n", pulse, dat);
178228

229+
if (TYPE34) {
230+
if (dat & 4)
231+
dpy_i = 7 - (dat & 7);
232+
else
233+
dpy_i = (dat & 3) + 4;
234+
sim_debug(DBG_IOT, &dpy_dev, "Set intensity to %06o\n", dpy_i);
235+
return dat;
236+
}
237+
179238
if (pulse & 001) {
180239
if (ty340_sense(ST340_LPHIT))
181240
dat |= IOT_SKP;
@@ -196,6 +255,9 @@ int32 dpy10 (int32 dev, int32 pulse, int32 dat)
196255
{
197256
sim_debug(DBG_IOT, &dpy_dev, "7010%02o, %06o\n", pulse, dat);
198257

258+
if (TYPE34)
259+
return dat;
260+
199261
if (pulse & 001) {
200262
if (ty340_sense(ST340_HEDGE))
201263
dat |= IOT_SKP;

linc/linc_tape.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@
4444
#define DBG_WRITE 0010
4545
#define DBG_POS 0020
4646

47-
static uint16 GROUP;
47+
static uint16 BLOCK_GROUP;
4848
static int16 CURRENT_BLOCK;
4949
static int16 WANTED_BLOCK;
5050

@@ -113,15 +113,15 @@ void tape_op(void)
113113
switch (C & 7) {
114114
case RDC: case RDE: case WRC: case WRI: case CHK:
115115
S = 256 * (B >> 9);
116-
GROUP = 0;
117-
sim_debug(DBG, &tape_dev, "Single tranfer: S=%04o, BN=%03o\n",
116+
BLOCK_GROUP = 0;
117+
sim_debug(DBG, &tape_dev, "Single transfer: S=%04o, BN=%03o\n",
118118
S, WANTED_BLOCK);
119119
break;
120120
case RCG: case WCG:
121121
S = 256 * (B & 7);
122-
GROUP = B >> 9;
122+
BLOCK_GROUP = B >> 9;
123123
sim_debug(DBG, &tape_dev, "Group transfer: S=%04o, BN=%03o/%o\n",
124-
S, WANTED_BLOCK, GROUP+1);
124+
S, WANTED_BLOCK, BLOCK_GROUP+1);
125125
break;
126126
case MTB:
127127
sim_debug(DBG, &tape_dev, "Move towards block %03o\n", WANTED_BLOCK);
@@ -232,12 +232,12 @@ static void tape_done(UNIT *uptr)
232232
paused = 0;
233233
break;
234234
case RCG: case WCG:
235-
if (GROUP == 0) {
235+
if (BLOCK_GROUP == 0) {
236236
sim_debug(DBG, &tape_dev, "Done with group\n");
237237
paused = 0;
238238
} else {
239-
sim_debug(DBG, &tape_dev, "Blocks left in group: %d\n", GROUP);
240-
GROUP--;
239+
sim_debug(DBG, &tape_dev, "Blocks left in group: %d\n", BLOCK_GROUP);
240+
BLOCK_GROUP--;
241241
}
242242
WANTED_BLOCK = (WANTED_BLOCK + 1) & TMASK;
243243
break;

scp.c

Lines changed: 4 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -9733,18 +9733,10 @@ for (rptr = lowr; rptr <= highr; rptr++) {
97339733
if ((idx > lows) && (val == last_val))
97349734
continue;
97359735
if (idx > val_start+1) {
9736-
if (idx-1 == val_start+1) {
9737-
reason = ex_reg (ofile, val, flag, rptr, idx-1);
9738-
sim_switches = saved_switches;
9739-
if (reason != SCPE_OK)
9740-
return reason;
9741-
}
9742-
else {
9743-
if (val_start+1 != idx-1)
9744-
fprintf (ofile, "%s[%d]-%s[%d]: same as above\n", rptr->name, val_start+1, rptr->name, idx-1);
9745-
else
9746-
fprintf (ofile, "%s[%d]: same as above\n", rptr->name, val_start+1);
9747-
}
9736+
if (val_start+1 != idx-1)
9737+
fprintf (ofile, "%s[%d]-%s[%d]: same as above\n", rptr->name, val_start+1, rptr->name, idx-1);
9738+
else
9739+
fprintf (ofile, "%s[%d]: same as above\n", rptr->name, val_start+1);
97489740
}
97499741
sim_last_val = last_val = val;
97509742
val_start = idx;

sim_card.c

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -33,9 +33,11 @@
3333
First characters 6789----
3434
Second character 21012345
3535
111
36-
Top 4 bits of second character are 0.
37-
It is unlikely that any other format could
38-
look like this.
36+
The lower order 4 bits of first word are all
37+
zero. It is unlikely that any other format could
38+
look like this. An ASCII card could match this
39+
if it is all blank, but the trailing return would
40+
cause it to fail this test.
3941
4042
BCD Format:
4143
Each record variable length (80 chars or less).

sim_card.h

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -30,12 +30,15 @@
3030
3131
Binary Card format:
3232
Each record 160 characters.
33-
First character 21012345
34-
111
35-
Second characters 6789----
36-
Top 4 bits of second character are 0.
37-
It is unlikely that ascii text or BCD format
38-
text could produce similar profile.
33+
First characters 6789----
34+
Second character 21012345
35+
111
36+
37+
The lower order 4 bits of first word are all
38+
zero. It is unlikely that any other format could
39+
look like this. An ASCII card could match this
40+
if it is all blank, but the trailing return would
41+
cause it to fail this test.
3942
4043
BCD Format:
4144
Each record variable length (80 chars or less).

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