interrupt

Author: larsbrinkhoff

linc/linc_cpu.c

@@ -29,6 +29,7 @@
 
 /* Debug */
 #define DBG_CPU         0001
+#define DBG_INT         0002
 
 #define WMASK  07777  /* Full word. */
 #define HMASK  04000  /* H bit; half word select. */
@@ -57,9 +58,9 @@ static uint16 XL[12];
 static int paused;
 static int IBZ;
 static int OVF;
+static int INTREQ;
+static int ENI = 0;
 static int PINFF;
-static int interrupt;
-static int interrupt_enable = 0;
 
 static t_stat stop_reason;
 
@@ -95,11 +96,16 @@ REG cpu_reg[] = {
   { ORDATAD(LSW, LSW, 12, "Left Switches") },
   { ORDATAD(RSW, RSW, 12, "Right Switches") },
   { ORDATAD(SSW, SSW,  6, "Sense Switches") },
+
   { FLDATAD(paused, paused, 1, "Paused") },
-  { FLDATAD(IBZ, IBZ,  1, "Interblock zone") },
-  { FLDATAD(OVF, OVF,  1, "Overflow") },
-  { BRDATAD(SAM, SAM,  8, 7, 16, "Sampled analog inputs") },
-  { BRDATAD(XL,  XL,   8, 1, 12, "External levels") },
+  { FLDATAD(IBZ,    IBZ,    1, "Interblock zone") },
+  { FLDATAD(OVF,    OVF,    1, "Overflow") },
+  { FLDATAD(INTREQ, INTREQ, 1, "Interrupt") },
+  { FLDATAD(ENI,    ENI,    1, "Interrupt Enable") },
+  { FLDATAD(PIN,    PINFF,  1, "Pause Interrupt") },
+
+  { BRDATAD(SAM,    SAM,    8, 7, 16, "Sampled analog inputs") },
+  { BRDATAD(XL,     XL,     8, 1, 12, "External levels") },
   { NULL }
 };
 
@@ -111,6 +117,7 @@ static MTAB cpu_mod[] = {
 
 static DEBTAB cpu_deb[] = {
   { "CPU", DBG_CPU },
+  { "INTERRUPT", DBG_INT },
   { NULL, 0 }
 };
 
@@ -218,7 +225,8 @@ cpu_misc(void)
     A = Z >> 1;
     break;
   case 00010: //ENI
-    interrupt_enable = 1;
+    sim_debug(DBG_INT, &cpu_dev, "ENI, Interrupt enabled.\n");
+    ENI = 1;
     break;
   case 00011: //CLR
     A = L = Z = 0;
@@ -232,6 +240,7 @@ cpu_misc(void)
     A = R & RMASK;
     break;
   case 00016: //NOP
+    sim_debug(DBG_CPU, &cpu_dev, "NOP\n");
     break;
   case 00017: //COM
     A = (~A) & WMASK;
@@ -336,6 +345,8 @@ int cpu_skip(void)
     break;
   case 046: //PIN
     flag = PINFF;
+    PINFF = 0;
+    sim_debug(DBG_INT, &cpu_dev, "PIN -> %d.\n", flag);
     break;
   case 050: //AZE
     flag = (A == 0) || (A == WMASK);
@@ -374,7 +385,10 @@ static void cpu_opr(void)
       ; //Pause.
     break;
   case 015: //KBD
+    sim_debug(DBG_CPU, &cpu_dev, "KBD%s\n", C & IMASK ? " i" : "");
     A = kbd_key(C & IMASK);
+    sim_debug(DBG_CPU, &cpu_dev, " key = %02o\n", A);
+    sim_debug(DBG_CPU, &cpu_dev, " paused = %d\n", paused);
     break;
   case 016: //RSW
     A = RSW;
@@ -721,12 +735,32 @@ cpu_insn(void)
   }
 
   /* Check for interrupts. */
-  if ((C & 06000) != 06000 && C != 00010 && interrupt && interrupt_enable) {
-    interrupt = interrupt_enable = 0;
+  if (INTREQ && ENI) {
+    sim_debug(DBG_INT, &cpu_dev,
+              "Interrupt requested and enabled; paused = %d.\n",
+              paused);
+    if ((C & 06000) == 06000 || C == 00010)
+      sim_debug(DBG_INT, &cpu_dev, "Can't interrupt after JMP or ENI.\n");
+  }
+  if ((C & 06000) != 06000 && C != 00010 && INTREQ && ENI) {
+    sim_debug(DBG_INT, &cpu_dev, "Interrupt taken.\n");
+    if (paused) {
+      PINFF = 1;
+      sim_debug(DBG_INT, &cpu_dev, "Was paused, set PINFF.\n");
+    }
+    paused = 0;
     memaddr(021);
     memrd();
     C = B;
-    cpu_jmp();
+    INTREQ = ENI = 0;
+    if ((C & 06000) == 06000) {
+      sim_debug(DBG_INT, &cpu_dev, "JMP in 21.\n");
+      cpu_jmp();
+    } else if ((C & 07700) == 00500) {
+      sim_debug(DBG_INT, &cpu_dev, "OPR in 21.\n");
+      cpu_opr();
+    } else if ((B & 07777) == 00016)
+      sim_debug(DBG_INT, &cpu_dev, "NOP in 21.\n");
   }
 }
 
@@ -739,6 +773,8 @@ t_stat sim_instr(void)
 
   stop_reason = 0;
   paused = 0;
+  PINFF = 0;
+  ENI = 0;
 
   for (;;) {
     AIO_CHECK_EVENT;
@@ -750,13 +786,18 @@ t_stat sim_instr(void)
     if (sim_brk_summ && sim_brk_test(P, SWMASK('E')))
       return STOP_IBKPT;
 
-#if 0
+#if 1
     if (paused)
       sim_debug(DBG_CPU, &cpu_dev, "Paused\n");
 #endif
-    if (paused)
+    if (paused) {
       sim_interval--;
-    else
+      if (INTREQ && ENI && !PINFF) {
+        sim_debug(DBG_INT, &cpu_dev, "Interrupt during pause\n");
+        paused = 0;
+        PINFF = 1;
+      }
+    } else
       cpu_insn();
 
     if (sim_step != 0) {

linc/linc_kbd.c

@@ -4,6 +4,9 @@
 /* Debug */
 #define DBG   0001
 
+#define A (*(uint16 *)cpu_reg[2].loc)
+#define paused (*(int *)cpu_reg[11].loc)
+
 static t_stat kbd_svc(UNIT *uptr);
 static t_stat kbd_reset(DEVICE *dptr);
 
@@ -222,8 +225,9 @@ uint16 kbd_key(uint16 wait)
     sim_activate_abs(&kbd_unit, 1);
     kbd_pressed = 0;
     return kbd_code;
-  } else {
+  } else if (wait) {
     sim_debug(DBG, &kbd_dev, "KEY paused\n");
+    paused = 1;
   }
   return 0;
 }
@@ -404,7 +408,11 @@ static void kbd_convert(uint32 key)
   }
   sim_debug(DBG, &kbd_dev, "Key struck %s -> %02o\n",
             vid_key_name(key), kbd_code);
-  kbd_pressed = 1;
+  if (paused)
+    A = kbd_code;
+  else
+    kbd_pressed = 1;
+  paused = 0;
 }
 
 static int

linc/tests/classic-test.do

@@ -73,7 +73,8 @@ call test 701 ZTAT1  115 105
 call test 702 ZCLR1  116 106
 deposit SAM[0] 177
 call test 703 ZCLRT2 117 107
-;call test 704 ENIT1  120 110
+deposit INTREQ 1
+call test 704 ENIT1  120 110
 deposit RSW 0300
 deposit LSW 0700
 deposit SSW 77