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mahavirjmahavirj
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Merge branch 'feature/clock_glitch_enable' into 'master'
bootloader: Enable clock glitch detection Closes IDF-2453, IDF-1720, IDFGH-5721, and IDFGH-5327 See merge request espressif/esp-idf!14868
2 parents 803c0bc + bf1dde7 commit d504ca6

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17 files changed

+250
-19
lines changed

17 files changed

+250
-19
lines changed

‎components/bootloader/subproject/main/ld/esp32/bootloader.ld

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ SECTIONS
4949
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
5050
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
5151
*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
52+
*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
5253
*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
5354
*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
5455
*libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)

‎components/bootloader/subproject/main/ld/esp32c3/bootloader.ld

Lines changed: 1 addition & 0 deletions
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@@ -36,6 +36,7 @@ SECTIONS
3636
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
3737
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
3838
*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
39+
*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
3940
*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
4041
*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
4142
*libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)

‎components/bootloader/subproject/main/ld/esp32h2/bootloader.ld

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@ SECTIONS
3636
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
3737
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
3838
*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
39+
*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
3940
*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
4041
*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
4142
*libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)

‎components/bootloader/subproject/main/ld/esp32s2/bootloader.ld

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@ SECTIONS
3636
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
3737
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
3838
*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
39+
*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
3940
*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
4041
*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
4142
*libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)

‎components/bootloader/subproject/main/ld/esp32s3/bootloader.ld

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@ SECTIONS
3737
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
3838
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
3939
*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
40+
*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
4041
*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
4142
*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
4243
*libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)

‎components/bootloader_support/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ if(BOOTLOADER_BUILD)
2626
"src/bootloader_console_loader.c"
2727
"src/bootloader_panic.c"
2828
"src/${IDF_TARGET}/bootloader_sha.c"
29+
"src/${IDF_TARGET}/bootloader_soc.c"
2930
"src/${IDF_TARGET}/bootloader_${IDF_TARGET}.c"
3031
)
3132
list(APPEND priv_requires hal)

‎components/bootloader_support/include_bootloader/bootloader_soc.h

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#pragma once
7+
8+
/**
9+
* @brief Configure analog super WDT reset
10+
*
11+
* @param enable Boolean to enable or disable super WDT reset
12+
*/
13+
void bootloader_ana_super_wdt_reset_config(bool enable);
14+
15+
/**
16+
* @brief Configure analog brownout reset
17+
*
18+
* @param enable Boolean to enable or disable brownout reset
19+
*/
20+
void bootloader_ana_bod_reset_config(bool enable);
21+
22+
/**
23+
* @brief Configure analog clock glitch reset
24+
*
25+
* @param enable Boolean to enable or disable clock glitch reset
26+
*/
27+
void bootloader_ana_clock_glitch_reset_config(bool enable);

‎components/bootloader_support/src/bootloader_utility.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@
7676
#include "bootloader_utility.h"
7777
#include "bootloader_sha.h"
7878
#include "bootloader_console.h"
79+
#include "bootloader_soc.h"
7980
#include "esp_efuse.h"
8081

8182
static const char *TAG = "boot";
@@ -636,6 +637,12 @@ static void load_image(const esp_image_metadata_t *image_data)
636637
ESP_LOGI(TAG, "Disabling RNG early entropy source...");
637638
bootloader_random_disable();
638639

640+
/* Disable glitch reset after all the security checks are completed.
641+
* Glitch detection can be falsely triggered by EMI interference (high RF TX power, etc)
642+
* and to avoid such false alarms, disable it.
643+
*/
644+
bootloader_ana_clock_glitch_reset_config(false);
645+
639646
// copy loaded segments to RAM, set up caches for mapped segments, and start application
640647
unpack_load_app(image_data);
641648
}

‎components/bootloader_support/src/esp32/bootloader_soc.c

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#include <stdbool.h>
7+
8+
void bootloader_ana_super_wdt_reset_config(bool enable)
9+
{
10+
(void)enable;
11+
}
12+
13+
void bootloader_ana_bod_reset_config(bool enable)
14+
{
15+
(void)enable;
16+
}
17+
18+
void bootloader_ana_clock_glitch_reset_config(bool enable)
19+
{
20+
(void)enable;
21+
}

‎components/bootloader_support/src/esp32c3/bootloader_esp32c3.c

Lines changed: 24 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "regi2c_ctrl.h"
3737
#include "bootloader_console.h"
3838
#include "bootloader_flash_priv.h"
39+
#include "bootloader_soc.h"
3940
#include "esp_efuse.h"
4041

4142
static const char *TAG = "boot.esp32c3";
@@ -263,18 +264,35 @@ static inline void bootloader_hardware_init(void)
263264
}
264265
}
265266

266-
static inline void bootloader_glitch_reset_disable(void)
267+
static inline void bootloader_ana_reset_config(void)
267268
{
268269
/*
269270
For origin chip & ECO1: only support swt reset;
270271
For ECO2: fix brownout reset bug, support swt & brownout reset;
271272
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
272273
*/
273274
uint8_t chip_version = bootloader_common_get_chip_revision();
274-
if (chip_version < 2) {
275-
REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST);
276-
} else if (chip_version == 2) {
277-
REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST);
275+
switch (chip_version) {
276+
case 0:
277+
case 1:
278+
//Enable WDT reset. Disable BOR and GLITCH reset
279+
bootloader_ana_super_wdt_reset_config(true);
280+
bootloader_ana_bod_reset_config(false);
281+
bootloader_ana_clock_glitch_reset_config(false);
282+
break;
283+
case 2:
284+
//Enable WDT and BOR reset. Disable GLITCH reset
285+
bootloader_ana_super_wdt_reset_config(true);
286+
bootloader_ana_bod_reset_config(true);
287+
bootloader_ana_clock_glitch_reset_config(false);
288+
break;
289+
case 3:
290+
default:
291+
//Enable WDT, BOR, and GLITCH reset
292+
bootloader_ana_super_wdt_reset_config(true);
293+
bootloader_ana_bod_reset_config(true);
294+
bootloader_ana_clock_glitch_reset_config(true);
295+
break;
278296
}
279297
}
280298

@@ -283,7 +301,7 @@ esp_err_t bootloader_init(void)
283301
esp_err_t ret = ESP_OK;
284302

285303
bootloader_hardware_init();
286-
bootloader_glitch_reset_disable();
304+
bootloader_ana_reset_config();
287305
bootloader_super_wdt_auto_feed();
288306
// protect memory region
289307
bootloader_init_mem();

‎components/bootloader_support/src/esp32c3/bootloader_soc.c

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#include <stdbool.h>
7+
#include "soc/soc.h"
8+
#include "soc/rtc_cntl_reg.h"
9+
10+
void bootloader_ana_super_wdt_reset_config(bool enable)
11+
{
12+
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
13+
14+
if (enable) {
15+
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
16+
} else {
17+
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
18+
}
19+
}
20+
21+
void bootloader_ana_bod_reset_config(bool enable)
22+
{
23+
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST);
24+
25+
if (enable) {
26+
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
27+
} else {
28+
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
29+
}
30+
}
31+
32+
void bootloader_ana_clock_glitch_reset_config(bool enable)
33+
{
34+
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);
35+
36+
if (enable) {
37+
REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
38+
} else {
39+
REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
40+
}
41+
}

‎components/bootloader_support/src/esp32h2/bootloader_esp32h2.c

Lines changed: 7 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "regi2c_ctrl.h"
3737
#include "bootloader_console.h"
3838
#include "bootloader_flash_priv.h"
39+
#include "bootloader_soc.h"
3940

4041
static const char *TAG = "boot.esp32h2";
4142

@@ -257,27 +258,20 @@ static inline void bootloader_hardware_init(void)
257258

258259
}
259260

260-
static inline void bootloader_glitch_reset_disable(void)
261+
static inline void bootloader_ana_reset_config(void)
261262
{
262-
/*
263-
For origin chip & ECO1: only support swt reset;
264-
For ECO2: fix brownout reset bug, support swt & brownout reset;
265-
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
266-
*/
267-
uint8_t chip_version = bootloader_common_get_chip_revision();
268-
if (chip_version < 2) {
269-
REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST);
270-
} else if (chip_version == 2) {
271-
REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST);
272-
}
263+
//Enable WDT, BOR, and GLITCH reset
264+
bootloader_ana_super_wdt_reset_config(true);
265+
bootloader_ana_bod_reset_config(true);
266+
bootloader_ana_clock_glitch_reset_config(true);
273267
}
274268

275269
esp_err_t bootloader_init(void)
276270
{
277271
esp_err_t ret = ESP_OK;
278272

279273
bootloader_hardware_init();
280-
bootloader_glitch_reset_disable();
274+
bootloader_ana_reset_config();
281275
bootloader_super_wdt_auto_feed();
282276
// protect memory region
283277
bootloader_init_mem();

‎components/bootloader_support/src/esp32h2/bootloader_soc.c

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#include <stdbool.h>
7+
#include "soc/soc.h"
8+
#include "soc/rtc_cntl_reg.h"
9+
10+
void bootloader_ana_super_wdt_reset_config(bool enable)
11+
{
12+
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
13+
14+
if (enable) {
15+
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
16+
} else {
17+
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
18+
}
19+
}
20+
21+
void bootloader_ana_bod_reset_config(bool enable)
22+
{
23+
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST);
24+
25+
if (enable) {
26+
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
27+
} else {
28+
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
29+
}
30+
}
31+
32+
void bootloader_ana_clock_glitch_reset_config(bool enable)
33+
{
34+
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);
35+
36+
if (enable) {
37+
REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
38+
} else {
39+
REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
40+
}
41+
}

‎components/bootloader_support/src/esp32s2/bootloader_soc.c

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#include <stdbool.h>
7+
8+
void bootloader_ana_super_wdt_reset_config(bool enable)
9+
{
10+
(void)enable;
11+
}
12+
13+
void bootloader_ana_bod_reset_config(bool enable)
14+
{
15+
(void)enable;
16+
}
17+
18+
void bootloader_ana_clock_glitch_reset_config(bool enable)
19+
{
20+
(void)enable;
21+
}

‎components/bootloader_support/src/esp32s3/bootloader_esp32s3.c

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434
#include "bootloader_mem.h"
3535
#include "bootloader_console.h"
3636
#include "bootloader_flash_priv.h"
37+
#include "bootloader_soc.h"
3738
#include "esp_efuse.h"
3839

3940

@@ -296,9 +297,18 @@ static void bootloader_super_wdt_auto_feed(void)
296297
REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
297298
}
298299

300+
static inline void bootloader_ana_reset_config(void)
301+
{
302+
//Enable WDT, BOR, and GLITCH reset
303+
bootloader_ana_super_wdt_reset_config(true);
304+
bootloader_ana_bod_reset_config(true);
305+
bootloader_ana_clock_glitch_reset_config(true);
306+
}
307+
299308
esp_err_t bootloader_init(void)
300309
{
301310
esp_err_t ret = ESP_OK;
311+
bootloader_ana_reset_config();
302312
bootloader_super_wdt_auto_feed();
303313
// protect memory region
304314
bootloader_init_mem();

‎components/bootloader_support/src/esp32s3/bootloader_soc.c

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#include <stdbool.h>
7+
#include "soc/soc.h"
8+
#include "soc/rtc_cntl_reg.h"
9+
10+
void bootloader_ana_super_wdt_reset_config(bool enable)
11+
{
12+
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
13+
14+
if (enable) {
15+
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
16+
} else {
17+
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
18+
}
19+
}
20+
21+
void bootloader_ana_bod_reset_config(bool enable)
22+
{
23+
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST);
24+
25+
if (enable) {
26+
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
27+
} else {
28+
REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);
29+
}
30+
}
31+
32+
void bootloader_ana_clock_glitch_reset_config(bool enable)
33+
{
34+
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST);
35+
36+
if (enable) {
37+
REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
38+
} else {
39+
REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN);
40+
}
41+
}

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