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HARSHDEEPSINGHBEDI/README.md

πŸ‘‹ Sat Shree Akaal, I'm Harshdeep Singh

🎯 Business Enthusiast | πŸ“Š Aspiring Analyst | πŸ’» Tech-Driven Thinker
πŸŽ“ B.Tech Electrical Engineering @ IIT Jammu (2026)
πŸ“ From Amritsar,Punjab | 🧩 Interning @ Amazon (BA Intern)


πŸ”— Connect With Me

LinkedIn
X (Twitter)
Linktree


πŸš€ Projects

πŸ”§ Processor Design & Implementation

Designed single-cycle, multi-cycle, and pipelined MIPS-32 processors in Verilog using Vivado.
β†’ Tools: Verilog, Vivado, Digital Logic Design

πŸŒ• Lunar Surface Elemental Mapping

Built high-res elemental maps of the moon using QGIS and remote sensing data for Inter IIT Tech Meet.
β†’ Tools: Python, QGIS, PyXspec

🧏 Audio Hearing Impairment Device

Created a real-time audio device that shifts inaudible frequencies into audible ranges.
β†’ Tools: Python, Signal Processing

🚦 Bosch Traffic Sign Recognition

Improved deep learning model accuracy to 92% using OpenCV and Keras on traffic datasets.
β†’ Tools: TensorFlow, Keras, OpenCV

🏠 House Price Prediction & Sentiment Analysis (Intern @ LearnFlow)

Developed ML models using regression and NLP techniques for real-world applications.
β†’ Tools: Random Forests, LSTM, Naive Bayes


πŸ“ˆ GitHub Stats

GitHub Stats


πŸ“« Let's Collaborate

I'm open to collaborating on AI/ML, semiconductor design, or analytics-driven projects.
Feel free to connect or drop a message!

Pinned Loading

  1. MIPS_Multicycle_Processor MIPS_Multicycle_Processor Public

    Part of my Computer Architecture Course

    Verilog

  2. MIPS_Pipelined MIPS_Pipelined Public

    Verilog

  3. MIPS_Single_Cycle_Processor MIPS_Single_Cycle_Processor Public

    Part of my Computer Architecture Course

    Verilog