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Tested on RX 6700 XT (RDNA2) at 4K/50% scale: 28-33 fps with the EASU+RCAS active (also running RX_VK_ASYNC=1 + RX_VK_BATCH=1 + RX_VK_PRESENT_QUEUE=1). The upscaler costs ~0.5ms GPU (measured 16.1ms/frame with EASU vs 15.5ms with bilinear). Visually: foliage edges and distant detail are noticeably sharper than bilinear. No artifacts observed. A/B revert via |
…olour space) Review on PR NotRexed#1439 (hckrman101), all four addressed: - taau_rcas.comp: the history bound tests (pc.valid & 1) only, as main's taau_upscale.comp after PR NotRexed#1115; the higher bits carry FXAA there and must never turn the bound on (first frame after a resize clamped against an unwritten hist). - vk_draw.cpp, readme: the FSR path replaces NotRexed#1115's FXAA, documented at the mode decision and in the readme's switches: RX_VK_TAAU_FXAA applies only with RX_VK_TAAU_MODE=bilinear; EASU's kernel does the edge work otherwise. - taau_easu/taau_rcas.comp: the sqrt decoding moved out of EASU's loads to a single square at RCAS's output (before the bound): FSR 1 runs on the perceptual encoding, its edge detection, luma weights and RCAS's 1 - mx4 term ([0,1]) now work in the space they were tuned for, and mid's B10G11R11 keeps more of the darks. spv headers regenerated (glslang 16.6.0). - tests/test_taau_env_lookup.py: the fixture's spies match the stand-in's current shape: ViewUse::Sample and VK_FORMAT_UNDEFINED in the spy, a view_type stub, Texture width/height, a 10-arg typed_upscale spy that checks the forwarded source size, and a no-resolved-input rejection case.
…olour space) Review on PR NotRexed#1439 (hckrman101), all four addressed: - taau_rcas.comp: the history bound tests (pc.valid & 1) only, as main's taau_upscale.comp after PR NotRexed#1115; the higher bits carry FXAA there and must never turn the bound on (first frame after a resize clamped against an unwritten hist). - vk_draw.cpp, readme: the FSR path replaces NotRexed#1115's FXAA, documented at the mode decision and in the readme's switches: RX_VK_TAAU_FXAA applies only with RX_VK_TAAU_MODE=bilinear; EASU's kernel does the edge work otherwise. - taau_easu/taau_rcas.comp: the sqrt decoding moved out of EASU's loads to a single square at RCAS's output (before the bound): FSR 1 runs on the perceptual encoding, its edge detection, luma weights and RCAS's 1 - mx4 term ([0,1]) now work in the space they were tuned for, and mid's B10G11R11 keeps more of the darks. spv headers regenerated (glslang 16.6.0). - tests/test_taau_env_lookup.py: the fixture's spies match the stand-in's current shape: ViewUse::Sample and VK_FORMAT_UNDEFINED in the spy, a view_type stub, Texture width/height, a 10-arg typed_upscale spy that checks the forwarded source size, and a no-resolved-input rejection case.
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Thanks for the thorough re-review! All four fixes are verified — I've addressed the two merge blockers:
The forced update is already on |
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…olour space) Review on PR NotRexed#1439 (hckrman101), all four addressed: - taau_rcas.comp: the history bound tests (pc.valid & 1) only, as main's taau_upscale.comp after PR NotRexed#1115; the higher bits carry FXAA there and must never turn the bound on (first frame after a resize clamped against an unwritten hist). - vk_draw.cpp, readme: the FSR path replaces NotRexed#1115's FXAA, documented at the mode decision and in the readme's switches: RX_VK_TAAU_FXAA applies only with RX_VK_TAAU_MODE=bilinear; EASU's kernel does the edge work otherwise. - taau_easu/taau_rcas.comp: the sqrt decoding moved out of EASU's loads to a single square at RCAS's output (before the bound): FSR 1 runs on the perceptual encoding, its edge detection, luma weights and RCAS's 1 - mx4 term ([0,1]) now work in the space they were tuned for, and mid's B10G11R11 keeps more of the darks. spv headers regenerated (glslang 16.6.0). - tests/test_taau_env_lookup.py: the fixture's spies match the stand-in's current shape: ViewUse::Sample and VK_FORMAT_UNDEFINED in the spy, a view_type stub, Texture width/height, a 10-arg typed_upscale spy that checks the forwarded source size, and a no-resolved-input rejection case.
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Rebased onto current main (4d68bc8) per review, as commit c3728dc. The readme change applied clean; gpu/vk/vk_draw.cpp needed conflict resolution, as on the v2.1.0-rc.3 rebase:
Update: the two Python test suites pass against the rebased tree with the llvm-mingw toolchain — test_upscale_fallback.py (all 23 cases) and test_taau_env_lookup.py. |
Joey-Magnus
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The c3728dc rebase is good: gpu/vk/vk_draw.cpp and readme.md merge cleanly with current main. The only conflict left is tests/test_taau_env_lookup.py, where #2042 rewrote the file to include hookshot_env.h and wrap env_on. Keep main's version and add your src_w/src_h spy changes on top. At the PR head, test_taau_fxaa, test_taau_env_lookup and test_upscale_fallback pass locally.
The blocker is CI. The title "gpu/vk: FSR 1 ..." fails the Conventional Commit check, so only that check has run, and the Windows and llvm-mingw builds of the new shaders have never been run. Something like feat(vk): FSR 1 EASU + RCAS in place of the bilinear TAAU stand-in would pass.
One thing to note before merge: taau_key picks the stand-in wherever mma_software is set (vk_coopmat.cpp). That covers AMD, Intel, the GTX 16xx cards and the Steam Deck, so FSR 1 replaces FXAA by default on every one of them. You measured 0.5 ms on a 6700 XT. A timing on the Deck or on an Intel iGPU would show the default is safe at the low end.
The bilinear stand-in on AMD loses all edge detail at 50% internal scale. This replaces it with FSR 1's EASU (12-tap edge-adaptive) and RCAS (5-tap contrast-capped sharpening) as two GLSL compute shaders wired into the existing taau_stand_in/typed_upscale interception. - gpu/vk/shaders/taau_easu.comp: EASU ported from the WGSL in rx_present_fx.cpp, 8x8 workgroups, reads RGB9E5, writes B10G11R11 - gpu/vk/shaders/taau_rcas.comp: RCAS with the stand-in's flash/NaN history clamp preserved - gpu/vk/vk_draw.cpp: typed_upscale builds three pipelines (sampler/ mid/dst/hist), EASU then RCAS dispatch with full_barrier between - Escape hatches: RX_VK_TAAU_MODE=bilinear (old path), RX_VK_TAAU_SHARPNESS=<stops> (default 0.2) - Measured on RX 6700 XT: ~0.5ms GPU cost, visually sharper than bilinear at the same resolution Co-authored-by: GLM-5.3 <noreply@z.ai>
…olour space) Review on PR NotRexed#1439 (hckrman101), all four addressed: - taau_rcas.comp: the history bound tests (pc.valid & 1) only, as main's taau_upscale.comp after PR NotRexed#1115; the higher bits carry FXAA there and must never turn the bound on (first frame after a resize clamped against an unwritten hist). - vk_draw.cpp, readme: the FSR path replaces NotRexed#1115's FXAA, documented at the mode decision and in the readme's switches: RX_VK_TAAU_FXAA applies only with RX_VK_TAAU_MODE=bilinear; EASU's kernel does the edge work otherwise. - taau_easu/taau_rcas.comp: the sqrt decoding moved out of EASU's loads to a single square at RCAS's output (before the bound): FSR 1 runs on the perceptual encoding, its edge detection, luma weights and RCAS's 1 - mx4 term ([0,1]) now work in the space they were tuned for, and mid's B10G11R11 keeps more of the darks. spv headers regenerated (glslang 16.6.0). - tests/test_taau_env_lookup.py: the fixture's spies match the stand-in's current shape: ViewUse::Sample and VK_FORMAT_UNDEFINED in the spy, a view_type stub, Texture width/height, a 10-arg typed_upscale spy that checks the forwarded source size, and a no-resolved-input rejection case.
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Rebased onto current main (ef81aee) as asked; the head is now 4876761, still the same two commits. Conflict resolved: only
Tests at 4876761, llvm-mingw clang++ (x86_64-w64-mingw32) on Windows:
Title: changed to Not done: the timing on a Steam Deck or an Intel iGPU. I only have the 6700 XT figure, so whether FSR 1 is a safe default at the low end (everywhere |
Joey-Magnus
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Both points from my last review are done: the title passes, and 4876761 merges cleanly with current main. I merged it into main and ran tests/run_all.py: 426 passed, and the only failure is test_lift_cache, which fails on main here too. test_taau_env_lookup, test_taau_fxaa and test_upscale_fallback all pass. CI's builds still haven't run because the workflows are waiting for approval, so the llvm-mingw build of the two new shaders is still unchecked.
The point still open is the default. typed_upscale now runs EASU+RCAS on every mma_software card (AMD, Intel, the GTX 16xx cards and the Deck), and in the generic RGB9E5 fallback too. That replaces #1115's FXAA on the strength of one 6700 XT timing. A number from a Deck or an Intel iGPU would settle it. Otherwise, keep FSR 1 opt-in until someone has one.
Smaller things:
- If pipe_easu or pipe_rcas fails to build, typed_upscale returns false and the network runs. Falling back to pipe_linear would keep the old stand-in instead.
- No test compares taau_easu_comp_spv.h or taau_rcas_comp_spv.h with their sources, the way test_taau_fxaa does for taau_upscale.
What
On AMD, the game's TAAU neural upscaler is replaced by a bilinear stand-in (HMMA cost issue #52). This replaces that bilinear with FSR 1's EASU (12-tap edge-adaptive) + RCAS (contrast-capped sharpening) as two GLSL compute shaders.
Why
Bilinear at 50% internal scale loses all edge detail — foliage smears, distant geometry loses definition. EASU preserves edges and detail at the same resolution with ~0.5ms GPU cost (measured on RX 6700 XT). The EASU/RCAS shader code was already in the repo (inherited from TOTKPort in
gpu/render/rx_present_fx.cpp) — this ports it to GLSL compute and wires it into the existing stand-in site.Changes
gpu/vk/shaders/taau_easu.comp(new) — FSR 1 EASU, 8×8 workgroups, reads RGB9E5, writes B10G11R11gpu/vk/shaders/taau_rcas.comp(new) — RCAS with the stand-in's flash/NaN history clamp preservedgpu/vk/vk_draw.cpp—typed_upscalebuilds three pipelines off one push-descriptor layout; EASU → barrier → RCASRX_VK_TAAU_MODE=bilinear(old path),RX_VK_TAAU_SHARPNESS=<stops>(default 0.2)Testing
RX_VK_TAAU_MODE=bilinearNote
This is quality-only — it won't raise fps in CPU-bound scenes (the frame is guest-emulation-bound). But it gives the 50% Resolution row a proper upscaler instead of a plain blit, at essentially zero GPU cost.
AI assistance disclosure: the EASU/RCAS port and pipeline wiring were developed with AI assistance, verified and tested by a human on the affected hardware.