[klimovich008]

What this fixes

Single-precision FMUL/FNMUL/FMLA results that the FPX1 fast path can't prove fell back to the soft-float exact body every time. These are tiny or infinite results, or a subnormal input under FZ. Code that runs with those cumulative FPSR flags already set paid that cost on each such op.

Why merge

The rescue keeps the hardware result only when it can raise no new FPSR bit. Everything else still goes to the exact body. The review found no correctness problem.

Change

• a64_fpx_sticky32 runs in the outlined wrappers a64_fpx_mul32_fma32 and a64_fpx_fma32_fma32, inside the gate.
• It uses RECOMP_FPX_FMA64; without a hardware FMA only FMUL is rescued.
• Cheap rejects run before any FP op.
• Dead fz_mul32 code is removed.
• The FPX1 contract comment now points to the wrappers.

Tested

tests/test_fpx_sticky.py builds at x86-64-v3 and x86-64-v2. Each build runs:

• guest FMUL/FNMUL/FMADD/FMLA S words through the lifter's pipeline (96 runs);
• 16M random checks;
• 150M sweep checks.

There were 0 mismatches against the exact body. Rescues are counted inside the wrappers, and a rescue under a closed gate fails the test. Sabotages of the emitter route, the wrapper route, the FIZ/AH/NEP mask and the UFC/IDC checks each fail it.

Not covered

• No Unicorn, insn or leaf test run.
• No full re-lift.
• No game re-measure of this revision.
• No aarch64, wasm or GCC build.
• The shadow build doesn't exercise the rescue.

🤖 Generated with Claude Code

[klimovich008]

Thanks. All seven points are addressed in 1ff4abe and 0a2b38e:

1. The wrappers now call A64_FPX_STICKY_PROBE() (empty by default) when the sticky rescue keeps a result, and the test counts those calls. A new lifted-route case runs hand-encoded FMUL, FNMUL, FMADD and FMLA S guest words through a64emit.translate and a64_lift.op_text/hot_text, the lifter's own pipeline. It checks the whole Ctx against the same words with FPX off, plus the probe count, on 5 must-rescue and 7 must-fall-back inputs. With the emitter no longer outlining FMUL (EmitFPMulAddValue), that case fails while the by-name runs pass. With fpx_header's tuple made never to match, every run fails.
2. There's a second build at -march=x86-64-v2 (-DEXPECT_FMA=0, #error if RECOMP_FPX_FMA64 disagrees). It needs only SSSE3, SSE4.2 and POPCNT, not AVX2. It requires FMUL rescues > 0 and FMLA rescues == 0: 16.5M / 0 in the sweep.
3. gen_state now sets FPCR bits 0-2. The sweep adds 16 states: partial IDC/UFC/OFC, IXC clear, and FIZ/AH/NEP. The exact body models none of FIZ/AH/NEP, so a rescue under a closed gate fails the test. Dropping bits 0-2 from the mask fails it (190k random and 6.1M sweep at v3).
4. The FPX1 comment in FpxH now points to the wrappers' rescues and says the shadow build doesn't reach them. Nothing moved into the runtime.
5. A64_FPX_FMA32 is gone; the helper uses RECOMP_FPX_FMA64.
6. Removed a64_fpx_fz_mul32, fz_result's mul and its branch, "mul32" in the elif, and the unused A64_FPX_FZ_OPEN. Comment updated.
7. One OPEN test per wrapper. Before any FP op, the rescue rejects NaN operands, FMLA without an FMA, and FMUL with OFC and UFC clear and nothing flushed. Rescue counts are unchanged, and the fallback microbenchmark is flat within noise.

Results: 2 × (16M random + 150M sweep + 96 lifted) checks, 0 mismatches.