- Introduction
- Types of Network Interface Cards
- Ethernet
- Working of Ethernet
- Design Phase
- 5.1 Introduction
- 5.2 Construction of the NIC Card
- 5.3 Implementation
- 5.3.1 Hardware Design
- 5.3.2 Software Design
- 5.4 What is JTAG?
- 5.5 What is Cross Compilation?
- 5.6 Design Procedure
- 5.7 Testing and Results
- 5.8 What is IP Core?
- Conclusion
- References
A Network Interface Card (NIC) is a hardware component, typically a circuit board or chip, installed on a computer to connect it to a network. NICs provide functionality such as I/O interrupt support, direct memory access (DMA) interfaces, data transmission, network traffic engineering, and partitioning.
The NIC uses the OSI model to send signals at the physical layer, transmit data packets at the network layer, and operate as an interface at the TCP/IP layer.
While the standard NIC is a plastic circuit board that slides into a computer to connect with the motherboard, there are multiple ways this connection can occur:
- Wireless NICs: Provide wireless reception through radio frequency waves.
- Wired NICs: Have input jacks for cables, with Ethernet being a popular wired LAN technology.
- USB NICs: Provide network connections through a device plugged into the USB port.
- Fibre Optics NICs: Expensive and complex NICs used for high-speed support in server computers.
Ethernet is a communication protocol created in 1973 that connects computers on a network over a wired connection. It is widely used for Local Area Networks (LANs) and Wide Area Networks (WANs).
Ethernet is still a common form of network connection used for its high speed, security, and reliability. It is employed in local networks, school campuses, hospitals, company offices, etc. Ethernet's low price contributed to its popularity compared to technologies like IBM's Token Ring.
Ethernet offers advantages such as high speed, reliability, and backward compatibility. It is fully backward compatible, providing consistent speed and reliability through cables. However, it requires wiring each room for Ethernet connectivity, limiting movement, and making troubleshooting complex if issues arise.
Ethernet follows a set of rules governing its basic operation. It uses the OSI model, with frames analogous to sentences in human language. Frames have explicit minimum and maximum lengths, destination and source addresses, and must follow specific rules for construction.
The OSI Reference Model is essential for understanding Ethernet and serves as a universal language for computer networking. It divides communication into seven abstract layers, each stacked upon the last.
The TCP/IP Model allows communication over large distances, offering a layered server architecture system. It complements the OSI Model and is crucial for real-time control.
TCP VS OSI Model
lwIP is a small implementation of the TCP/IP protocol suite, designed to reduce resource usage while providing a full-scale TCP. It is suitable for embedded systems with limited RAM and code ROM.
The implementation platform chosen is a development board with a Virtex-5 FPGA, specifically the ML507. Using the Xilinx Platform Studio (XPS) tool, the embedded PowerPC 440 processor is configured inside the Virtex-5 FPGA for designing the NIC card.
Xilinx ML-507 Evaluation Board
The NIC card construction involves various modules connected to the PowerPC (processor) on the FPGA. It includes components like memory chips,RS232, Ethernet MAC, and a DDR_SDRAM memory device.
Hardware design components include PowerPC 440, Block RAM, interrupt controller, RS232, Ethernet MAC, and a DDR_SDRAM memory device.
Software design is configured using the Software Development Kit (SDK), and a C-program is written for the server that works on TCP data.
Joint Test Action Group (JTAG) is a standard interface and protocol used between a PC and a device (like an FPGA) for testing, programming, and debugging.
Cross compilation is the process of compiling code on one platform and running it on a different platform. It is often used in embedded systems development.
The design procedure involves configuring the PowerPC, connecting modules, implementing hardware and software designs, and testing the system.
Absolutely, here's the information with image mentions using the provided links:
- Opening XPS Platform Studio and Naming the Project
- After opening the XPS Platform Studio using the BSB wizard, the project is named in the directory where it is created.
- The project is stored along with the selection of the PLB system.
- Creating a New Design
- If the user has a midway completed project or a project with changes needed, they can import the .BSB file to work on it.
- Selected Development Board Display
- The selected development board is displayed, and if it is a standard board, its specifications are automatically uploaded and fixed.
- System Configuration Window
- Here, the user decides whether it is a single or dual processor system.
- Processor Configuration Window
- In this window, the user decides the clock of the processor and bus. It is crucial to ensure the bus and processor run on the same clock.
- Peripheral Configuration Window
- This window is used to specify which inbuilt modules are to be used and remove unnecessary ones.
- Cache Configuration Window
- Since the project does not require the use of cache, it is disabled. The system uses a Harvard architecture.
- Project Generation with BSB Wizard
- Click the Finish button to finish generating the project. If something is missed or any peripheral needs to be added, it can be done by right-clicking a section in the description box and then clicking add.
- System Assembly View
- In this view, the user can see the list of components
- Addressing for the Peripherals/Modules
- This section displays the addressing used by each of the components. Users can lock the addresses.
- Port Declaration for the Peripherals/Modules
- Here, users can see which components use which ports.
- Bus Interfaces for the Peripherals/Modules
- This section illustrates how each component is connected to the PLB bus system.
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Implementing the Design
- After generating the project using the BSB wizard, the design is implemented in the "Implement Flow" section by running it through "Generate Netlist," "Generate Bitstream," and then exporting the design into SDK to create the software.
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Hardware Platform Specifications in SDK Window
- After uploading the project to SDK, users can see hardware platform specifications.
- New Application Project Creation Window
- Users can create a new application project, selecting the language (C or C++).
- Template Selection - lwIP Echo Server
- In the template selection, the lwIP Echo server is chosen.
- Generating Linker Script
- Users can generate the linker script to view the address and size allocated for memory components. They can also increase the heap and stack size if needed.
- Including lwIP Library in Boards Manager
- Users need to include the lwIP library in the Boards Manager to avoid errors during compilation.
Following the outlined design procedure and utilizing the JTAG for boundary scan through the Impact tool, the implementation of Ethernet on the FPGA has been successfully executed. The testing phase involves using the "ping" command to validate IP-level connectivity between the FPGA and a computer.
The "ping" command is employed to verify IP-level connectivity to another TCP/IP computer. This is achieved by sending Internet Control Message Protocol (ICMP) echo Request messages, and the corresponding echo Reply messages are received and displayed, along with round-trip times. The "ping" command serves as a primary TCP/IP tool for troubleshooting connectivity, reachability, and name resolution. When used without parameters, the command displays Help content.
The request is initiated from the PC and sent to the FPGA through an Ethernet cable. The FPGA responds back with the information, which is displayed in the command line. This establishes a successful server-client system between the FPGA and a computer via Ethernet.
- Screenshot 1
- Screenshot 2
In these screenshots, the configuration of the lwIP TCP Echo server is visible, along with the responses from the FPGA board to the continuous "ping" commands. The information is displayed as long as the connection remains intact.
- Screenshot 3
- Screenshot 4
These screenshots illustrate the behavior when the Ethernet cable is disconnected. When the connection is disrupted, a "General Failure" message is displayed. Upon reconnecting the cable, the information is promptly restored, indicating the resumption of connectivity.
- Screenshot 5
This screenshot shows the continuous monitoring of the connection status. The information reflects the dynamic nature of the connection, instantly responding to cable disconnection and reconnection events.
An Intellectual Property (IP) Core is a reusable unit of logic, cell, or chip layout design that can be easily integrated into a larger design.
The objective of implementing Ethernet NIC communication on FPGA was successfully achieved. The tools used include Xilinx tools (XPS, SDK, IMPACT) and Tera Term. The project successfully establishes a server-client system between the ML507 development board and a PC via Ethernet.
- www.xilinx.com
- "The Design Warrior's Guide to FPGAs" - Book by Clive Maxfield
- www.google.in
- researchgate.net/publication/350483427_What_You_Need_to_Know_About_Smart_Network_Interface_Cards
- geeksforgeeks.org/what-is-cross-compiler/
- www.mouser.in/blog/three-things-you-should-know-about-ethernet-phy
- www.wikipedia.com
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