The issue is with a flip flop where the check test signal is supposed to force a DC Set (IIRC), but there is also a reset input active - it was a matter of DC set/reset priorities. It might be a simple matter of changing the priorities on that particular gate - if it doesn't affect other uses of that gate.
The issue is with a flip flop where the check test signal is supposed to force a DC Set (IIRC), but there is also a reset input active - it was a matter of DC set/reset priorities. It might be a simple matter of changing the priorities on that particular gate - if it doesn't affect other uses of that gate.