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[RISCV] Miscompilation of inline assembly #100779

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@shkoo

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@shkoo

It looks like LLC is miscompiling passing a register load to inline assembly:

target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32"

@_ZN5repro9MY_BUFFER17hb0f674501d5980a6E = external global <{ [16 x i8] }>

define void @using_inout() {
start:
  %0 = tail call ptr asm sideeffect alignstack "ecall", "=&{x10},0,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(ptr @_ZN5repro9MY_BUFFER17hb0f674501d5980a6E)
  ret void
}

Running llc on this crashes with assertions enabled (https://godbolt.org/z/1zWaoxKKE).

Without assertions, it generates incorrect code (https://godbolt.org/z/43c4W44nY); notice that it silently discards the load of the low bits of _ZN5repro9MY_BUFFER17hb0f674501d5980a6E causing an incorrect value to be loaded in register a0:

using_inout:                            # @using_inout
        lui     a0, %hi(_ZN5repro9MY_BUFFER17hb0f674501d5980a6E)
        ecall
        ret

This regression looks like it happened somewhere between llvm 17 (https://godbolt.org/z/o6eWGx68o) and llvm 18 (https://godbolt.org/z/fMMd9Gf3W).

For more background, see rust-lang/rust#128212

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