Fix incorrect LoRA weight loading for fused gate_up_proj

[lifuhuang]

Motivation

During testing, I identified two bugs introduced in my previous PR for supporting phi-4-mm.

1. (Major impact) I introduced fused LoRA weight support in my prev PR, however, I did not correctly handle gate_up_proj shape. This problem was not caught earlier because pytorch implicitly handled shape mismatch through broadcast.

2. (Minor impact) I had an incorrect understanding of the seqlens calculation for Idefics embedding. When tgt_sizes is absent, input_embeds should not have been masked. Reference: https://github.com/vllm-project/vllm/blob/fd7bb88d72ba721d6eb4f9d34198ad930c36c177/vllm/model_executor/models/idefics2_vision_model.py#L34

MMMU score for phi4 mm increased from 47 to 53.1 after these two fixes, consistent with vLLM (difference within random error). Both vLLM and SGLang are slightly lower than the benchmark reported in the original paper, but the difference might be due to different sampling params or benchmark script.

Framework	MMMU
SGLang	53.1
vLLM	52.5
original paper	55

Modification

1. Reshape gate_up_proj to conform to the current convention.
2. Correct the seqlens calculation for Idefics embedding.

Checklist

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[lifuhuang]

Hi @lifuhuang , is there any accuracy improvement with this PR?

Updated description. MMMU_val for phi4mm increased from 47 to 53, mostly in par with the official benchmark (55). The majority of the gain was coming from the bug fix for LoRA shape. Thank you for catching it in my last PR :)

[Fridge003]

LGTM