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SIMD test IR not ASM #82078

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9ca0e14
Older iOS / watchOS targets do not default to having armv8.2 FP16 ena…
stephentyrone Jun 6, 2025
a74988f
Revert "Older iOS / watchOS targets do not default to having armv8.2 …
stephentyrone Jun 6, 2025
f942827
Replace SIMD tests that look at assembly with IR.
stephentyrone Jun 7, 2025
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95 changes: 37 additions & 58 deletions test/stdlib/SIMDFloatComparisons.swift.gyb
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Original file line number Diff line number Diff line change
Expand Up @@ -11,13 +11,18 @@
//===----------------------------------------------------------------------===//
// RUN: %empty-directory(%t)
// RUN: %gyb %s -o %t/SIMDFloatComparisons.swift
// RUN: %target-swift-frontend -primary-file %t/SIMDFloatComparisons.swift -S | %FileCheck %t/SIMDFloatComparisons.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECKOnone-%target-cpu
// RUN: %target-swift-frontend -primary-file %t/SIMDFloatComparisons.swift -S -O | %FileCheck %t/SIMDFloatComparisons.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECKO-%target-cpu
// RUN: %target-swift-frontend -primary-file %t/SIMDFloatComparisons.swift -emit-ir | %FileCheck %t/SIMDFloatComparisons.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu

import Swift

%for bits in [16,32,64]:
% if bits == 16:
% arch = "-arm64"
% else:
% arch = ""
% end
% scalar = {16:'Float16',32:'Float',64:'Double'}[bits]
% llvm = {16:'half',32:'float',64:'double'}[bits]
% for totalBits in [64,128]:
% n = totalBits // bits
% if n != 1:
Expand All @@ -33,16 +38,12 @@ func compare_eq${n}x${bits}(
}
% if bits == 16:
#endif
// CHECK-arm64: compare_eq${n}x${bits}{{[[:alnum:]_]+}}:
% else:
// CHECK: compare_eq${n}x${bits}{{[[:alnum:]_]+}}:
// CHECK-x86_64: cmpeqp${'s' if bits == 32 else 'd'}
// CHECK-x86_64: ret
% end
// CHECKO-arm64-NEXT: fcmeq.${neonSuffix} v0, v0, v1
// CHECKO-arm64-NEXT: ret
// CHECKOnone-arm64: fcmeq.${neonSuffix}
// CHECKOnone-arm64: ret
// CHECK${arch}: compare_eq${n}x${bits}{{.*}} {
// CHECK${arch}: entry:
// CHECK${arch}: [[TMP:%[0-9]+]] = fcmp oeq <${n} x ${llvm}> %0, %1
// CHECK${arch}-NEXT: [[RES:%[0-9]+]] = sext <${n} x i1> [[TMP]] to <${n} x i${bits}>
// CHECK${arch}-NEXT: ret <${n} x i${bits}> [[RES]]

% if bits == 16:
#if arch(arm64)
Expand All @@ -55,18 +56,12 @@ func compare_ne${n}x${bits}(
}
% if bits == 16:
#endif
// CHECK-arm64: compare_ne${n}x${bits}{{[[:alnum:]_]+}}:
% else:
// CHECK: compare_ne${n}x${bits}{{[[:alnum:]_]+}}:
// CHECK-x86_64: cmpneqp${'s' if bits == 32 else 'd'}
// CHECK-x86_64: ret
% end
// CHECKO-arm64-NEXT: fcmeq.${neonSuffix} [[TMP:v[0-9]+]], v0, v1
// CHECKO-arm64-NEXT: mvn.${totalBits//8}b v0, [[TMP]]
// CHECKO-arm64-NEXT: ret
// CHECKOnone-arm64: fcmeq.${neonSuffix}
// CHECKOnone-arm64: mvn.${totalBits//8}b
// CHECKOnone-arm64: ret
// CHECK${arch}: compare_ne${n}x${bits}{{.*}} {
// CHECK${arch}: entry:
// CHECK${arch}: [[TMP:%[0-9]+]] = fcmp une <${n} x ${llvm}> %0, %1
// CHECK${arch}-NEXT: [[RES:%[0-9]+]] = sext <${n} x i1> [[TMP]] to <${n} x i${bits}>
// CHECK${arch}-NEXT: ret <${n} x i${bits}> [[RES]]

% if bits == 16:
#if arch(arm64)
Expand All @@ -79,16 +74,12 @@ func compare_lt${n}x${bits}(
}
% if bits == 16:
#endif
// CHECK-arm64: compare_lt${n}x${bits}{{[[:alnum:]_]+}}:
% else:
// CHECK: compare_lt${n}x${bits}{{[[:alnum:]_]+}}:
// CHECK-x86_64: cmpltp${'s' if bits == 32 else 'd'}
// CHECK-x86_64: ret
% end
// CHECKO-arm64-NEXT: fcmgt.${neonSuffix} v0, v1, v0
// CHECKO-arm64-NEXT: ret
// CHECKOnone-arm64: fcmgt.${neonSuffix}
// CHECKOnone-arm64: ret
// CHECK${arch}: compare_lt${n}x${bits}{{.*}} {
// CHECK${arch}: entry:
// CHECK${arch}: [[TMP:%[0-9]+]] = fcmp olt <${n} x ${llvm}> %0, %1
// CHECK${arch}-NEXT: [[RES:%[0-9]+]] = sext <${n} x i1> [[TMP]] to <${n} x i${bits}>
// CHECK${arch}-NEXT: ret <${n} x i${bits}> [[RES]]

% if bits == 16:
#if arch(arm64)
Expand All @@ -101,16 +92,12 @@ func compare_le${n}x${bits}(
}
% if bits == 16:
#endif
// CHECK-arm64: compare_le${n}x${bits}{{[[:alnum:]_]+}}:
% else:
// CHECK: compare_le${n}x${bits}{{[[:alnum:]_]+}}:
// CHECK-x86_64: cmplep${'s' if bits == 32 else 'd'}
// CHECK-x86_64: ret
% end
// CHECKO-arm64-NEXT: fcmge.${neonSuffix} v0, v1, v0
// CHECKO-arm64-NEXT: ret
// CHECKOnone-arm64: fcmge.${neonSuffix}
// CHECKOnone-arm64: ret
// CHECK${arch}: compare_le${n}x${bits}{{.*}} {
// CHECK${arch}: entry:
// CHECK${arch}: [[TMP:%[0-9]+]] = fcmp ole <${n} x ${llvm}> %0, %1
// CHECK${arch}-NEXT: [[RES:%[0-9]+]] = sext <${n} x i1> [[TMP]] to <${n} x i${bits}>
// CHECK${arch}-NEXT: ret <${n} x i${bits}> [[RES]]

% if bits == 16:
#if arch(arm64)
Expand All @@ -123,16 +110,12 @@ func compare_ge${n}x${bits}(
}
% if bits == 16:
#endif
// CHECK-arm64: compare_ge${n}x${bits}{{[[:alnum:]_]+}}:
% else:
// CHECK: compare_ge${n}x${bits}{{[[:alnum:]_]+}}:
// CHECK-x86_64: cmplep${'s' if bits == 32 else 'd'}
// CHECK-x86_64: ret
% end
// CHECKO-arm64-NEXT: fcmge.${neonSuffix} v0, v0, v1
// CHECKO-arm64-NEXT: ret
// CHECKOnone-arm64: fcmge.${neonSuffix}
// CHECKOnone-arm64: ret
// CHECK${arch}: compare_ge${n}x${bits}{{.*}} {
// CHECK${arch}: entry:
// CHECK${arch}: [[TMP:%[0-9]+]] = fcmp oge <${n} x ${llvm}> %0, %1
// CHECK${arch}-NEXT: [[RES:%[0-9]+]] = sext <${n} x i1> [[TMP]] to <${n} x i${bits}>
// CHECK${arch}-NEXT: ret <${n} x i${bits}> [[RES]]

% if bits == 16:
#if arch(arm64)
Expand All @@ -145,16 +128,12 @@ func compare_gt${n}x${bits}(
}
% if bits == 16:
#endif
// CHECK-arm64: compare_gt${n}x${bits}{{[[:alnum:]_]+}}:
% else:
// CHECK: compare_gt${n}x${bits}{{[[:alnum:]_]+}}:
// CHECK-x86_64: cmpltp${'s' if bits == 32 else 'd'}
// CHECK-x86_64: ret
% end
// CHECKO-arm64-NEXT: fcmgt.${neonSuffix} v0, v0, v1
// CHECKO-arm64-NEXT: ret
// CHECKOnone-arm64: fcmgt.${neonSuffix}
// CHECKOnone-arm64: ret
// CHECK${arch}: compare_gt${n}x${bits}{{.*}} {
// CHECK${arch}: entry:
// CHECK${arch}: [[TMP:%[0-9]+]] = fcmp ogt <${n} x ${llvm}> %0, %1
// CHECK${arch}-NEXT: [[RES:%[0-9]+]] = sext <${n} x i1> [[TMP]] to <${n} x i${bits}>
// CHECK${arch}-NEXT: ret <${n} x i${bits}> [[RES]]

% end
% end
Expand Down
60 changes: 16 additions & 44 deletions test/stdlib/SIMDFloatInitializers.swift.gyb
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Original file line number Diff line number Diff line change
Expand Up @@ -11,13 +11,18 @@
//===----------------------------------------------------------------------===//
// RUN: %empty-directory(%t)
// RUN: %gyb %s -o %t/SIMDFloatInitializers.swift
// RUN: %target-swift-frontend -primary-file %t/SIMDFloatInitializers.swift -S | %FileCheck %t/SIMDFloatInitializers.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECKOnone-%target-cpu
// RUN: %target-swift-frontend -primary-file %t/SIMDFloatInitializers.swift -S -O | %FileCheck %t/SIMDFloatInitializers.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECKO-%target-cpu
// RUN: %target-swift-frontend -primary-file %t/SIMDFloatInitializers.swift -emit-ir | %FileCheck %t/SIMDFloatInitializers.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu

import Swift

%for bits in [16,32,64]:
% if bits == 16:
% arch = "-arm64"
% else:
% arch = ""
% end
% scalar = {16:'Float16',32:'Float',64:'Double'}[bits]
% llvm = {16:'half',32:'float',64:'double'}[bits]
% for totalBits in [64,128]:
% n = totalBits // bits
% if n != 1:
Expand All @@ -31,51 +36,18 @@ func repeating${n}x${bits}(_ scalar: ${scalar}) -> SIMD${n}<${scalar}> {
}
% if bits == 16:
#endif
// CHECK-arm64: repeating${n}x${bits}{{[[:alnum:]_]+}}:
% end

// CHECK${arch}: repeating${n}x${bits}{{.*}} {
// CHECK${arch}: entry:
// CHECK${arch}: [[TMP:%[0-9]+]] = insertelement <${n} x ${llvm}> {{.*}} ${llvm} %0, i32 0
// CHECK${arch}-NEXT: [[REP:%[0-9]+]] = shufflevector <${n} x ${llvm}> [[TMP]], <${n} x ${llvm}> {{.*}}, <${n} x i32> zeroinitializer
% if totalBits == 64:
// CHECK-arm64-NEXT: ret <${n} x ${llvm}> [[REP]]
% else:
// CHECK: repeating${n}x${bits}{{[[:alnum:]_]+}}:
// CHECK${arch}-NEXT: ret <${n} x ${llvm}> [[REP]]
% end
// CHECKO-arm64-NEXT: dup.${neonSuffix} v0, v0[0]
// CHECKO-arm64-NEXT: ret
// CHECKOnone-arm64: dup.${neonSuffix}
// CHECKOnone-arm64: ret

% end
% end
%end

#if arch(arm64)
@available(macOS 11.0, iOS 14.0, tvOS 14.0, watchOS 7.0, *)
func concat4x16(_ a: SIMD4<Float16>, _ b: SIMD4<Float16>) -> SIMD8<Float16> {
SIMD8(lowHalf: a, highHalf: b)
}
// CHECK-arm64: s21SIMDFloatInitializers10concat4x16ys5SIMD8Vys7Float16VGs5SIMD4VyAFG_AJtF:
// CHECKO-arm64-NEXT: mov.d v0[1], v1[0]
// CHECKO-arm64-NEXT: ret

@available(macOS 11.0, iOS 14.0, tvOS 14.0, watchOS 7.0, *)
func concat8x16(_ a: SIMD8<Float16>, _ b: SIMD8<Float16>) -> SIMD16<Float16> {
SIMD16(lowHalf: a, highHalf: b)
}
// CHECK-arm64: s21SIMDFloatInitializers10concat8x16ys6SIMD16Vys7Float16VGs5SIMD8VyAFG_AJtF:
// CHECKO-arm64-NEXT: ret
#endif

func concat2x32(_ a: SIMD2<Float>, _ b: SIMD2<Float>) -> SIMD4<Float> {
SIMD4(lowHalf: a, highHalf: b)
}
// CHECK: s21SIMDFloatInitializers10concat2x32ys5SIMD4VySfGs5SIMD2VySfG_AHtF:
// CHECKO-arm64-NEXT: mov.d v0[1], v1[0]
// CHECKO-arm64-NEXT: ret

func concat4x32(_ a: SIMD4<Float>, _ b: SIMD4<Float>) -> SIMD8<Float> {
SIMD8(lowHalf: a, highHalf: b)
}
// CHECK: s21SIMDFloatInitializers10concat4x32ys5SIMD8VySfGs5SIMD4VySfG_AHtF:
// CHECKO-arm64-NEXT: ret

func concat2x64(_ a: SIMD2<Double>, _ b: SIMD2<Double>) -> SIMD4<Double> {
SIMD4(lowHalf: a, highHalf: b)
}
// CHECK: s21SIMDFloatInitializers10concat2x64ys5SIMD4VySdGs5SIMD2VySdG_AHtF:
// CHECKO-arm64-NEXT: ret
18 changes: 10 additions & 8 deletions test/stdlib/SIMDMaskInitializers.swift.gyb
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,7 @@
//===----------------------------------------------------------------------===//
// RUN: %empty-directory(%t)
// RUN: %gyb %s -o %t/SIMDMaskInitializers.swift
// RUN: %target-swift-frontend -primary-file %t/SIMDMaskInitializers.swift -S | %FileCheck %t/SIMDMaskInitializers.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECKOnone-%target-cpu
// RUN: %target-swift-frontend -primary-file %t/SIMDMaskInitializers.swift -S -O | %FileCheck %t/SIMDMaskInitializers.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECKO-%target-cpu
// RUN: %target-swift-frontend -primary-file %t/SIMDMaskInitializers.swift -emit-ir | %FileCheck %t/SIMDMaskInitializers.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu

import Swift

Expand All @@ -24,12 +23,15 @@ import Swift
func repeating${n}_mask${bits}(_ scalar: Bool) -> SIMDMask<SIMD${n}<Int${bits}>> {
SIMDMask(repeating: scalar)
}
// CHECK: repeating${n}_mask${bits}{{[[:alnum:]_]+}}:
// CHECKO-arm64-NEXT: sbfx [[REG:[wx][0-9]]], {{[wx]}}0, #0, #1
// CHECKO-arm64-NEXT: dup.${neonSuffix} v0, [[REG]]
// CHECKO-arm64-NEXT: ret
// CHECKOnone-arm64: dup.${neonSuffix}
// CHECKOnone-arm64: ret
// CHECK: repeating${n}_mask${bits}{{.*}} {
// CHECK: entry:
// CHECK: [[TMP:%[0-9]+]] = insertelement <${n} x i${bits}> {{.*}}, i${bits} %{{.*}}, i32 0
// CHECK-NEXT: [[REP:%[0-9]+]] = shufflevector <${n} x i${bits}> [[TMP]], <${n} x i${bits}> {{.*}}, <${n} x i32> zeroinitializer
% if totalBits == 64:
// CHECK-arm64-NEXT: ret <${n} x i${bits}> [[REP]]
% else:
// CHECK-NEXT: ret <${n} x i${bits}> [[REP]]
% end

% end
% end
Expand Down
66 changes: 10 additions & 56 deletions test/stdlib/SIMDSignedInitializers.swift.gyb
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,7 @@
//===----------------------------------------------------------------------===//
// RUN: %empty-directory(%t)
// RUN: %gyb %s -o %t/SIMDSignedInitializers.swift
// RUN: %target-swift-frontend -primary-file %t/SIMDSignedInitializers.swift -S | %FileCheck %t/SIMDSignedInitializers.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECKOnone-%target-cpu
// RUN: %target-swift-frontend -primary-file %t/SIMDSignedInitializers.swift -S -O | %FileCheck %t/SIMDSignedInitializers.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu --check-prefix=CHECKO-%target-cpu
// RUN: %target-swift-frontend -primary-file %t/SIMDSignedInitializers.swift -emit-ir | %FileCheck %t/SIMDSignedInitializers.swift --check-prefix=CHECK --check-prefix=CHECK-%target-cpu

import Swift

Expand All @@ -25,60 +24,15 @@ import Swift
func repeating${n}_int${bits}(_ scalar: Int${bits}) -> SIMD${n}<Int${bits}> {
SIMD${n}(repeating: scalar)
}
// CHECK: repeating${n}_int${bits}{{[[:alnum:]_]+}}:
// CHECKO-arm64-NEXT: dup.${neonSuffix} v0, {{[wx]}}0
// CHECKO-arm64-NEXT: ret
// CHECKOnone-arm64: dup.${neonSuffix}
// CHECKOnone-arm64: ret
// CHECK: repeating${n}_int${bits}{{.*}} {
// CHECK: entry:
// CHECK: [[TMP:%[0-9]+]] = insertelement <${n} x i${bits}> {{.*}}, i${bits} %0, i32 0
// CHECK-NEXT: [[REP:%[0-9]+]] = shufflevector <${n} x i${bits}> [[TMP]], <${n} x i${bits}> {{.*}}, <${n} x i32> zeroinitializer
% if totalBits == 64:
// CHECK-arm64-NEXT: ret <${n} x i${bits}> [[REP]]
% else:
// CHECK-NEXT: ret <${n} x i${bits}> [[REP]]
% end
% end
% end
%end

func concat8x8(_ a: SIMD8<Int8>, _ b: SIMD8<Int8>) -> SIMD16<Int8> {
SIMD16(lowHalf: a, highHalf: b)
}
// CHECK: s22SIMDSignedInitializers9concat8x8ys6SIMD16Vys4Int8VGs5SIMD8VyAFG_AJtF:
// CHECKO-arm64-NEXT: mov.d v0[1], v1[0]
// CHECKO-arm64-NEXT: ret
// CHECKO-x86_64: punpcklqdq

func concat16x8(_ a: SIMD16<Int8>, _ b: SIMD16<Int8>) -> SIMD32<Int8> {
SIMD32(lowHalf: a, highHalf: b)
}
// CHECK: s22SIMDSignedInitializers10concat16x8ys6SIMD32Vys4Int8VGs6SIMD16VyAFG_AJtF:
// CHECKO-arm64-NEXT: ret

func concat4x16(_ a: SIMD4<Int16>, _ b: SIMD4<Int16>) -> SIMD8<Int16> {
SIMD8(lowHalf: a, highHalf: b)
}
// CHECK: s22SIMDSignedInitializers10concat4x16ys5SIMD8Vys5Int16VGs5SIMD4VyAFG_AJtF:
// CHECKO-arm64-NEXT: mov.d v0[1], v1[0]
// CHECKO-arm64-NEXT: ret
// CHECKO-x86_64: punpcklqdq

func concat8x16(_ a: SIMD8<Int16>, _ b: SIMD8<Int16>) -> SIMD16<Int16> {
SIMD16(lowHalf: a, highHalf: b)
}
// CHECK: s22SIMDSignedInitializers10concat8x16ys6SIMD16Vys5Int16VGs5SIMD8VyAFG_AJtF:
// CHECKO-arm64-NEXT: ret

func concat2x32(_ a: SIMD2<Int32>, _ b: SIMD2<Int32>) -> SIMD4<Int32> {
SIMD4(lowHalf: a, highHalf: b)
}
// CHECK: s22SIMDSignedInitializers10concat2x32ys5SIMD4Vys5Int32VGs5SIMD2VyAFG_AJtF:
// CHECKO-arm64-NEXT: mov.d v0[1], v1[0]
// CHECKO-arm64-NEXT: ret
// CHECKO-x86_64: punpcklqdq

func concat4x32(_ a: SIMD4<Int32>, _ b: SIMD4<Int32>) -> SIMD8<Int32> {
SIMD8(lowHalf: a, highHalf: b)
}
// CHECK: s22SIMDSignedInitializers10concat4x32ys5SIMD8Vys5Int32VGs5SIMD4VyAFG_AJtF:
// CHECKO-arm64-NEXT: ret

func concat2x64(_ a: SIMD2<Int64>, _ b: SIMD2<Int64>) -> SIMD4<Int64> {
SIMD4(lowHalf: a, highHalf: b)
}
// CHECK: s22SIMDSignedInitializers10concat2x64ys5SIMD4Vys5Int64VGs5SIMD2VyAFG_AJtF:
// CHECKO-arm64-NEXT: ret

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