* edid-decode changed from 42f5fa4 to 3a6108a * 3a6108a - edid-decode: Add Dell UP3218K DP tiled edid <Clint Taylor> * ad20c30 - edid-decode: improve DisplayID 1.2/3 parsing <Hans Verkuil> * 31a3417 - edid-decode: add warn() function <Hans Verkuil> * 8752afd - edid-decode: improve some of the texts <Hans Verkuil> * 8f7bb1f - edid-decode: improve readability of output <Hans Verkuil> * dc8afbf - edid-decode: add new HDMI 2.1 Amendment A1 and HDR10+ support <Hans Verkuil> * 44d1587 - edid-decode: add more EDIDs <Hans Verkuil> * 7d26052 - edid-decode: improve "Invalid Detailed Timings" message <Hans Verkuil> * 0da30bd - edid-decode: Avoid division by zero <Breno Leitao> * ea15b91 - edid-decode: add ELO 4600L EDID <Hans Verkuil> * 7696439 - Add LG 32UD99-W edid from the DP (USB-C) input <Hans Verkuil> * 0932dee - Add LG 32UD99-W edid from the HDMI input <Hans Verkuil> * 3bd8bbe - Add EDID for LG OLED55E6V <Hans Verkuil> * d5fb521 - Add an EDID for the Samsung UE48JU7090 <Hans Verkuil> * flash_proxies changed from 1c21ee4 to 01d8f81 * 01d8f81 - remove bscan_spi_xcku040-sayma <Sebastien Bourdeauducq> * litedram changed from 6c53996 to 401554f * 401554f - Merge pull request #92 from gsomlo/gls-assert-width <enjoy-digital> |\ | * 7356d3b - frontend/wishbone: add base_address param. to LiteDRAMWishbone2Native <Gabriel Somlo> | * 24203cf - frontend/axi: add assertion on matching axi, native port data_width <Gabriel Somlo> |/ * d84e1b4 - frontend/axi: add assert on axi.address_width and base_address <Florent Kermarrec> * 1d037d2 - frontend/axi: add base_address parameter to LiteDRAMAXI2Native <Florent Kermarrec> * 5d1a984 - core: add LiteDRAMCore (ControllerInjector from LiteX) <Florent Kermarrec> * d647abd - gen: fix with_wishbone <Florent Kermarrec> * db97203 - gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore <Florent Kermarrec> * adf481f - gen: disable peripherals that are not used when cpu_type is None <Florent Kermarrec> * 2331919 - gen: change CSR config names, switch to csr_expose/csr_align <Florent Kermarrec> * da408a3 - gen: fix default csr_port_align value <Florent Kermarrec> * bac66aa - gen: In conjunction with the corresponding changes in litex itself, this will allow us to generate a more useful standalone litedram core. <Benjamin Herrenschmidt> * afbf709 - We had the address and data bus sizes mixed up <Benjamin Herrenschmidt> * d93dded - frontend/wishbone: add data_width assertions <Florent Kermarrec> * f586aad - phys: improve presentation (add separators, better indent) <Florent Kermarrec> * 783258c - phys: use dfi instead if self.dfi internally <Florent Kermarrec> * 59c1289 - phy/usddrphy: move DDR4DFIMux to dfi.py <Florent Kermarrec> * f861d99 - core/refresher: improve naming/parameters of refresh postponing <Florent Kermarrec> * dc1bb53 - phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common <Florent Kermarrec> * 509f606 - README: add periodic refresh/ZQ short calibration. <Florent Kermarrec> * 40b4c62 - test/test_init: fix <Florent Kermarrec> * 5b48eb2 - test/test_init: delete generated file <Florent Kermarrec> * 188b6a8 - add ZQ periodic short calibration support (default to 1s) <Florent Kermarrec> * 6e176d4 - init: split by memtype <Florent Kermarrec> * 0b24b81 - test: add test_init with sdr/ddr3/ddr4 references <Florent Kermarrec> * bf5883c - rename sdram_init to init <Florent Kermarrec> * 23ccdc9 - modules: add DDR3 MT8KTF51264 SO-DIMM <Florent Kermarrec> * d37a30e - litedram_gen: add wishbone user port support <Florent Kermarrec> * b6a0eff - frontend/wishbone: split control/data paths (to avoid data muxes) <Florent Kermarrec> * 6497343 - frontend/wishbone: remove IDLE fsm state <Florent Kermarrec> * 00ecb87 - gen: add separators <Florent Kermarrec> * a782eb5 - test/test_examples: adapt for travis <Florent Kermarrec> * f678efa - travis: add pyyaml <Florent Kermarrec> * 8861d80 - Merge pull request #91 from sd-fritze/master <enjoy-digital> |\ | * fe2cc94 - modules: Add support for Micron MT47H32M16 DDR2 RAM <gruetzkopf> |/ * a23b9e7 - core/refresher: set cmd.valid to 0 when sequencer done <Florent Kermarrec> * 12ddc13 - litedram/gen: add description and switch to argparse <Florent Kermarrec> * 2bdeda0 - move standalone core generation to litedram package and make it usable externally <Florent Kermarrec> * 0dde125 - examples/litedram_gen: fix #!/usr/bin/env python3 location <Florent Kermarrec> * 602ff8b - examples: switch to YAML config files <Florent Kermarrec> * fb28f79 - core/refresher: remove load/load_count on RefreshTimer (not used) <Florent Kermarrec> * 1c69f49 - core/controller: allow user provided Refresher <Florent Kermarrec> * b64daba - core/controller: add separators, ease readibility <Florent Kermarrec> * 338d18d - core/refresher: add capability to accumulate N refreshs and execute the N refreshs together <Florent Kermarrec> * 818c4ca - core/refresher: another cleanup pass <Florent Kermarrec> * 80c8ecf - core/multiplexer: rewrite arbiter comment <Florent Kermarrec> * 37db416 - core/refresher: another cleanup pass <Florent Kermarrec> * f0592ff - core/refresher: add comments <Florent Kermarrec> * de38b52 - core/refresher: rename RefreshGenerator to RefreshSequencer and simplify <Florent Kermarrec> * 8573c22 - phy/gensdrphy: add assertions on length of pads.dq/pads.dq <Florent Kermarrec> * liteeth changed from ad187d3 to 4d9e74f * 4d9e74f - phy/usrgmii: cleanup (style, indent) <Florent Kermarrec> * 4bc79ce - examples/targets/core: update <Florent Kermarrec> * cd0eaa9 - Merge pull request #19 from jersey99/master <enjoy-digital> * 59e0460 - Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940 <Vamsi K Vytla> * litepcie changed from 71c9a3a to 47e76f4 * 47e76f4 - example/dma: keep up to date with litex <Florent Kermarrec> * 7f9367c - example/make: keep up to date with litex <Florent Kermarrec> * c6a536a - frontend/dma: add optional underflows/overflows monitoring, rename tx_fifo/rx_fifo to reader_fifo/writer_fifo <Florent Kermarrec> * 6bb4a60 - frontend/dma/buffering: expose fifo levels to CSRs <Florent Kermarrec> * litescope changed from 9e3b9d8 to 7a9fa9d * 7a9fa9d - core: use new CSRStatus.we signal to speed-up Storage upload (>10x speedup over ethernet) <Florent Kermarrec> * 284253d - core: add csr_csv parameter and export csv_csv on do_exit <Florent Kermarrec> * 69a8df0 - Merge pull request #14 from DurandA/master <enjoy-digital> * 06cac3a - Use cpu instead of cpu_or_bridge in examples <Arnaud Durand> * litevideo changed from 98e145f to 49bafa4 * 49bafa4 - input/dma: no longer use aligment_bits of CSRStorage <Florent Kermarrec> * litex changed from v0.1-1099-ge637aa65 to v0.1-1333-ga54b80b9 * a54b80b9 - targets: use type="io" instead of io_region=True <Florent Kermarrec> * a0c0a6fd - integration/SoCMemRegion: use type instead of io_region/linker_region and export type to csv/json <Florent Kermarrec> * 9fcf2973 - soc_core: add check_regions_overlap method, add linker_region support (overlap is not checked on linker_regions) <Florent Kermarrec> * 4014fbff - soc_core/add_memory_region: fix memory overlap detection <Florent Kermarrec> * 650df0eb - test/test_targets: skip Minerva test on Travis-CI, remove commented tests <Florent Kermarrec> * ab8af282 - cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier <Florent Kermarrec> * 4cc40aad - Merge pull request #286 from gsomlo/gls-timingstrict <enjoy-digital> |\ | * 49372852 - build/lattice/trellis: optionally allow failure if p&r timing not met <Gabriel Somlo> |/ * b6d35c92 - Merge pull request #283 from kbeckmann/kbeckmann/bios_increment_address <enjoy-digital> |\ | * ef78ae95 - bios: Increment address when writing to flash <Konrad Beckmann> * | 683e0668 - build/lattice/trellis: use --timing-allow-fail to allow generating bistream when timings are not met <Florent Kermarrec> * | 4cf346a1 - soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1 <Florent Kermarrec> * | 39862f06 - Merge pull request #282 from antmicro/icapbitstream_fixes <enjoy-digital> |\ \ | * | 8b5da9c6 - cores/icap/ICAPBitstream: add source ready signal. <Jan Kowalewski> |/ / * | 626533ce - soc/integration/__init__: remove imports (not used and causing issues <Florent Kermarrec> * | 675b4552 - build: always use platform.add_source and avoid manipulate platform.sources directly <Florent Kermarrec> * | 43f5d1ef - build/generic_platform: replace set with list for sources/verilog_include_paths <Florent Kermarrec> * | 97a77b95 - cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it. <Florent Kermarrec> * | 98c224be - build/generic_platform: keep language to None if None after tools.language_by_filename <Florent Kermarrec> * | 14dae8bd - soc_core: fix default --uart_name <Florent Kermarrec> * | ba264418 - integration/soc_core: expose more SoC parameters <Florent Kermarrec> * | 23d83961 - Merge pull request #280 from kbeckmann/picorv32_typo <Tim Ansell> |\ \ | |/ |/| | * 0e467168 - picorv32: Fix minimal variant params <Konrad Beckmann> |/ * ef504f62 - soc_core: fix soc_core_argdict <Florent Kermarrec> * cd8213b9 - cpu/lm32: add missing buses <Florent Kermarrec> * 5a035875 - soc_core/soc_core_argdict: use inspect to get all parameters and simplify <Florent Kermarrec> * 96c369f3 - integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo) <Florent Kermarrec> * 29e51f5e - interconnect/wishbone: fix Converter case when buses are identical <Florent Kermarrec> * ae9c25b7 - platforms/versa_ecp5: add serdes refclk/sma <Florent Kermarrec> * 9a829338 - cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore) <Florent Kermarrec> * ca81cc20 - soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed) <Florent Kermarrec> * 03faf06c - soc/interconnect/axi: re-align to improve readability <Florent Kermarrec> * 7dea9afd - software/bios: simplify banners <Florent Kermarrec> * 6bd18893 - cpu/picorv32: remove obsolete comment <Florent Kermarrec> * 28517d20 - cpu/picorv32: use a single idbus <Florent Kermarrec> * 5daf1a22 - cpu: cleanup/re-align <Florent Kermarrec> * 467d35ed - cpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix <Florent Kermarrec> * 1045cda3 - cpu: add buses list and use it in soc_core to add bus masters <Florent Kermarrec> * 42ccc91f - integration: move soc constants to soc.h of csr.h <Florent Kermarrec> * ed3c53d7 - build/generic_platform: only add sources if language is not None <Florent Kermarrec> * f3ba0788 - xilinx/vivado: replace "xy" == language with language == "xy" <Florent Kermarrec> * 17756f63 - Merge pull request #277 from railnova/feature/vivado_sysverilog_support <enjoy-digital> |\ | * f2369a4c - Add system Verilog support for the Vivado builder <Martin Cornil> * | b2519482 - integration/soc_zynq: shadow_base no longer recommended (replace with io_regions) <Florent Kermarrec> * | 496ba7e5 - bios/main: use same banner than README (MiSoC cited in README/LICENSE) <Florent Kermarrec> * | 840f01b6 - software/bios: don't show peripherals init banner if nothing to init, add Ethernet init printf <Florent Kermarrec> |/ * 37531cec - Merge pull request #276 from gsomlo/gls-rocket-map <enjoy-digital> |\ | * f8f643a0 - cpu/rocket: swap main_mem and io regions <Gabriel Somlo> |/ * b627a8fe - cpu: add default io_regions to CPUNone (all address range can be used as IO) <Florent Kermarrec> * cc245fc8 - Merge pull request #275 from pcotret/patch-1 <enjoy-digital> |\ | * e923a88d - Update README (related to issue #273) <Pascal Cotret> * | a6b3aa3c - soc_core: improve check_io_region error message <Florent Kermarrec> * | dc656d48 - targets/sim: switch from shadow_base to io_regions <Florent Kermarrec> * | 10146abf - cpu/rocket: move csr to IO region <Florent Kermarrec> * | 7f1d4623 - build/xilinx/vivado: fix default synth-mode <Florent Kermarrec> * | a4ef9b29 - soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat) <Florent Kermarrec> |/ * e8b90e80 - Merge pull request #274 from gsomlo/gls-shadow-base <enjoy-digital> |\ | * 53777391 - builder: use the SoC's existing shadow base with get_csr_header() <Gabriel Somlo> |/ * 92975b13 - targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys <Florent Kermarrec> * 4a1cefe9 - build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode <Florent Kermarrec> * 3e22d4b9 - xilinx/common: be sure language is not vhdl when yosys synthesis is used <Florent Kermarrec> * 975bd9be - cpu/vexriscv: use specific mem_map for linux variant <Florent Kermarrec> * 2dfe7441 - Merge pull request #271 from gsomlo/gls-yosys-nowidelut <enjoy-digital> |\ | * 6aa76b1d - trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5 <Gabriel L. Somlo> * | c954ff0c - Merge pull request #272 from sergachev/fix-comments <enjoy-digital> |\ \ | |/ |/| | * 2f7bd971 - fix comments <Ilia Sergachev> * | ab4a5d1d - litex_setup: add litejesd204b <Florent Kermarrec> |/ * 960b25a5 - Merge pull request #270 from gsomlo/gls-csr-upper <enjoy-digital> |\ | * c8790d34 - soc/integration: ensure CSR constants are in uppercase <Gabriel Somlo> * | 41ad08e8 - soc/cores/icap: simplify ICAPBitstream (untested) <Florent Kermarrec> * | 0c299386 - soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP <Florent Kermarrec> * | 4bb2827e - Merge pull request #269 from antmicro/rework_icap <enjoy-digital> |\ \ | |/ |/| | * 4423a46b - soc: cores: support sending custom bitstream to ICAP <Jan Kowalewski> * | 427d7af7 - soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) <Florent Kermarrec> * | 59bf04d9 - soc/interconnect/stream: add separators, mode Actor modules just after Endpoint <Florent Kermarrec> * | 59995c53 - soc_zynq: update get_csr_header <Florent Kermarrec> * | 4d90058b - soc/integration: move cpu_interface retro-compatibility to litex/__init__ <Florent Kermarrec> * | 8be5824e - soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses <Florent Kermarrec> * | 7b72148c - cpu: remove initial SERV support (we'll work in a branch to experiment with it) <Florent Kermarrec> * | 63a813af - soc_core: fix cpu_type=None case and add test for it <Florent Kermarrec> * | 3d257d72 - soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests. <Florent Kermarrec> * | e8e57b4f - soc_core: cleanup/re-align <Florent Kermarrec> * | 334ae336 - soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators <Florent Kermarrec> * | 241c3c64 - test/test_targets: update cpu-type to mor1kx <Florent Kermarrec> * | 48e5a1d1 - soc/cores: uniformize (continue) <Florent Kermarrec> * | e9ed4761 - soc/cores/gpio: uniformize with others cores <Florent Kermarrec> * | 78cecbe3 - soc/cores: rename frequency_meter to freqmeter and uniformize with others cores <Florent Kermarrec> * | 7575ecc6 - soc/cores/ecc: improve readibility, uniformize with others cores <Florent Kermarrec> * | c6fe3f31 - soc/cores/clocks: improve readibility <Florent Kermarrec> * | 6fcb12a9 - soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround) <Florent Kermarrec> * | b826c170 - soc/cores/cpus: improve ident/align, uniformize between cpus <Florent Kermarrec> * | 355072c2 - soc/cores/cpu: add CPU class and make all CPU inheritate from it <Florent Kermarrec> * | 2c3ad3f9 - soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore) <Florent Kermarrec> * | 101f1b1c - soc/integration: add common.py and move helpers from soc_core to it <Florent Kermarrec> * | 68ba1c60 - soc_core: avoid manual listing of support CPUs, just use CPU.keys() <Florent Kermarrec> * | 9095b80e - soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change) <Florent Kermarrec> * | 8dd2dc1c - integration/soc_core: remove csr_map_update (no longer used) <Florent Kermarrec> * | da91aa43 - soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done <Florent Kermarrec> * | 8099b0be - soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter <Florent Kermarrec> * | 7660dc22 - soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated) <Florent Kermarrec> * | a3816096 - cores/cpu: define CPUS and simplify instance <Florent Kermarrec> * | 9f6a2ae7 - soc_core/serv: use UART_POLLING (no interrupt support) <Florent Kermarrec> * | a4069fc8 - add SERV submodule <Florent Kermarrec> * | 49594ed7 - software/libbase/uart: add polling mode <Florent Kermarrec> * | 3f95b9c0 - add SERV CPU initial support (not working) <Florent Kermarrec> * | 015b65fe - targets/ulx3s: revert to cl=2 <Florent Kermarrec> * | a9d55b04 - boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out <Florent Kermarrec> * | 1425a68d - wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) <Florent Kermarrec> * | ffd2be2b - csr: add we signal to CSR, CSRStatus <Florent Kermarrec> * | 47dc3324 - build/xilinx/programmer: fix vivado_cmd <Florent Kermarrec> * | ed9bff2e - soc/integration/doc: replace "== None" by "is None" <Florent Kermarrec> * | 836d5b88 - Merge pull request #266 from xobs/add-moduledoc-autodoc <enjoy-digital> |\ \ | * | 68cea8c3 - timer: inherit ModuleDoc <Sean Cross> | * | 13197198 - integration: add ModuleDoc and AutoDoc <Sean Cross> * | | 78fb0fb9 - tools/litex_read_verilog: also delete yosys_v2j.ys <Florent Kermarrec> * | | 0ea7a1fd - soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty <Benjamin Herrenschmidt> * | | 742da31b - Merge pull request #264 from antmicro/mor1kx_linux <enjoy-digital> |\ \ \ | * | | 5844376d - soc_core: adapt memory map for mainline Linux with mor1kx <Filip Kokosinski> | * | | 201218b2 - boards/targets: increase integrated ROM size if EthernetSoC is used <Filip Kokosinski> * | | | 06d08064 - soc_core: set csr to 0x00000000 when there is no wishbone <Florent Kermarrec> * | | | ad8830d9 - soc_sdram: Don't add the L2 Cache when there's no wishbone bus <Florent Kermarrec> |/ / / * | | ae38fd42 - soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter <Florent Kermarrec> * | | 8c979565 - soc_sdram: change l2_size checks order <Florent Kermarrec> * | | a9acab99 - soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals) <Florent Kermarrec> * | | dde6dd02 - integration/builder: avoid specific _generate_standalone_includes <Florent Kermarrec> * | | 735ea196 - This will allow it to be built for microwatt out of tree <Benjamin Herrenschmidt> * | | c28086cd - soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc... <Benjamin Herrenschmidt> * | | f909e4d7 - integration/builder: When the CPU is "None", we used to not generate any code. <Benjamin Herrenschmidt> |/ / * | 8b7d8217 - Merge pull request #263 from xobs/spi-flash-csrfield <enjoy-digital> |\ \ | * | 1a6dddd5 - spi_flash: document register fields <Sean Cross> |/ / * | 4f659ba4 - Merge pull request #262 from jersey99/master <enjoy-digital> |\ \ | * | 9ea11cf5 - vivado just needs to be in the path for the programmer as well <Vamsi K Vytla> |/ / * | 430fee4d - Merge pull request #261 from xobs/event-documentation <enjoy-digital> |\ \ | |/ |/| | * 60d8572c - csr_eventmanager: add `name` and `description` args <Sean Cross> |/ * e2c78572 - cores/timer: add general documentation on Timer implementation and behavior. <Florent Kermarrec> * e97c1e36 - soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower <Florent Kermarrec> * 99ed0877 - csr: add description to CSRStorage/CSRStatus attributes (thanks xobs) <Florent Kermarrec> * f2e84a58 - soc/cores/timer: fix typo (thanks xobs) <Florent Kermarrec> * 28885064 - soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident. <Florent Kermarrec> * f1139c36 - Merge pull request #259 from xobs/document-timer <enjoy-digital> |\ | * cb7d941a - timer: add documentation <Sean Cross> |/ * cca0478a - soc/cores/spi: use new CSRField (no functional change) <Florent Kermarrec> * 80b2bef3 - soc/cores/bitbang: use new CSRField (no functional change) <Florent Kermarrec> * 3dc8d294 - Merge pull request #257 from enjoy-digital/csr_fields <enjoy-digital> |\ | * 9bda614a - csr: update copyrights <Florent Kermarrec> | * 29134cc6 - csr: more documentation <Florent Kermarrec> | * 74e756aa - csr/CSRStorage: remove storage_full (was only needed by alignment_bits) <Florent Kermarrec> | * 5dc440e8 - csr: use IntEnum for CSRAccess <Florent Kermarrec> | * d2646f13 - csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful <Florent Kermarrec> | * 8e14694e - csr/fields: document, add separators, 100 characters per line <Florent Kermarrec> | * 4e84729c - csr/fields: add access parameter <Florent Kermarrec> | * 23b01f8f - csr/fields: add pulse mode support <Florent Kermarrec> | * 8c080e5f - soc/interconnect/csr: add initial field support <Florent Kermarrec> |/ * c120f6d4 - build/openocd: add set_qe parameter to flash <Florent Kermarrec> * 6a0a1c9d - tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example) <Florent Kermarrec> * 16b6b357 - soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found <Florent Kermarrec> * 62f53d50 - soc/integration/builder: call do_exit with vns when build is done. <Florent Kermarrec> * cb5f1467 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec> |\ | * a7b5c185 - Merge pull request #255 from sergachev/fix-crc32 <enjoy-digital> | |\ | | * 2400f0f4 - fix crc32 <Ilia Sergachev> | |/ * | 004c96b5 - soc/itnegration: update litedram <Florent Kermarrec> |/ * 19f58dd9 - interconnect/wishbone: add FlipFlop to allow UpConverter to be used <Florent Kermarrec> * bd6ec63b - build/openocd: add stream method for JTAG UART <Florent Kermarrec> * b356204f - soc_core: add JTAG UART support (uart_name="jtag_uart) <Florent Kermarrec> * d0ebbda4 - soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) <Florent Kermarrec> * 2638393b - soc_zynq: fix indent <Florent Kermarrec> * 9051cf97 - soc_zynq: fix typo <Florent Kermarrec> * 67a09aef - soc/interconnect/stream: add Monitor module <Florent Kermarrec> * 6f150a56 - Merge pull request #254 from mithro/crc-smaller <enjoy-digital> |\ | * 2a41f0d2 - Use `SMALL_CRC` to enable smaller CRC versions. <Tim 'mithro' Ansell> | * 08333744 - Remove extra whitespace. <Tim 'mithro' Ansell> | * c0e72386 - libbase: crc16: commit smaller version of crc16 <Sean Cross> | * a59d0efc - libbase: crc32: add smaller version <Sean Cross> * | 27c334d4 - Merge pull request #252 from mithro/only-change-on-contents <Tim Ansell> |\ \ | |/ |/| | * 3ff6a18a - Only write file if contents will change. <Tim 'mithro' Ansell> |/ * a2938a7a - soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" <Florent Kermarrec> * 19d3acfc - Merge pull request #251 from micro-FPGA/master <enjoy-digital> |\ | * fb00ee85 - Create atlantic.py <Antti Lukats> | * 92e5b4b2 - Merge pull request #2 from enjoy-digital/master <Antti Lukats> | |\ | * | f47e4978 - libero enable enhanced constraints <Antti Lukats> * | | 41fe7cae - core/spi: add minimal SPISlave <Florent Kermarrec> * | | b8457559 - gen/fhdl/verilog: allow single element verilog inline attribute <Florent Kermarrec> * | | 5a7b4c34 - targets/nexys_video: generate clk100 <Florent Kermarrec> * | | c179741c - software/bios: switch to standard CRLF <Florent Kermarrec> * | | 0328ba7d - tools/litex_term: add automatic check to see if we need to insert LF or not <Florent Kermarrec> * | | ffebd207 - bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available) <Florent Kermarrec> * | | 4842bdcf - tools/litex_term: add sdl_payload_length <Florent Kermarrec> * | | 3e30c648 - litex_setup: add litex-boards <Florent Kermarrec> * | | d79cd87d - Merge pull request #246 from gsomlo/gls-native-rv64 <enjoy-digital> |\ \ \ | * | | 6d844a03 - software: use native toolchain for same host, target architectures <Gabriel L. Somlo> |/ / / * | | d36f1fb7 - Merge pull request #244 from atommann/master <enjoy-digital> |\ \ \ | |_|/ |/| | | * | a45dbee5 - changing http to https <atommann> | * | 1d957d7a - Update .gitmodules <atommann> * | | 4990bf33 - soc/core: simplify/cleanup HyperRAM core - rename core to hyperbus. - change layout (cs_n with variable length instead of cs0_n, cs1_n). - use DifferentialOutput when differential clock is used. - add test (python3 -m unittest test.test_hyperbus). <Florent Kermarrec> * | | d1502d41 - soc/cores: add initial simple hyperram core <Antti Lukats> | |/ |/| * | 6e6fe83a - build/altera/quartus: add add_ip method to use Quartus QSYS files <Florent Kermarrec> * | 2899928a - cpu_interface: add json csr map export, simplify csv csr map export using json <Florent Kermarrec> * | 9d4b7cd5 - bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) <Florent Kermarrec> * | 0cd4e45f - build/xilinx/vivado: use "" for strings <Florent Kermarrec> * | 8d161a47 - build/xilinx/vivado: remove with_phys_opt <Florent Kermarrec> * | f6638ded - Merge pull request #243 from sergachev/master <enjoy-digital> |\ \ | * | 861eea8a - build/xilinx/vivado: improve directive support <Ilia Sergachev> * | | ccc2cbd9 - Merge pull request #241 from railnova/zynq <enjoy-digital> |\ \ \ | |/ / |/| | | * | db4c609a - [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat <chmousset> |/ / * | 6d5fddc1 - cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) <Florent Kermarrec> * | 383c05e2 - Merge pull request #240 from danielkucera/patch-1 <enjoy-digital> |\ \ | |/ |/| | * a5eaf172 - more understandable error when missing a memory <Daniel Kucera> |/ * 2b815f70 - Merge pull request #235 from gsomlo/gls-trellis-yosys-opt <enjoy-digital> |\ | * 6c298cb7 - build/lattice/trellis: use abc9 techmapping pass with yosys <Gabriel L. Somlo> |/ * 31bfb546 - software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys <Florent Kermarrec> * e670cb91 - cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus <Florent Kermarrec> * 6d94c07d - software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle <Florent Kermarrec> * 0c287b11 - cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap <Florent Kermarrec> * 82cd557c - software/bios: add Ethernet PHY MDIO read/write/dump commands <Florent Kermarrec> * 0ba9ab92 - altera/common: fix AsyncResetSynchronizer polarity and simplify <Florent Kermarrec> * 124dff8f - build/xilinx/common: improve presentation <Florent Kermarrec> * 60873a5b - microsemi/common: improve presentation <Florent Kermarrec> * 36d9d78c - build/altera/common: improve presentation <Florent Kermarrec> * 95953d29 - platforms/default_clk_period: use 1e9/freq <Florent Kermarrec> * f1d8c70b - targets/minispartan6/crg: only keep S6PLL code <Florent Kermarrec> * d3d0a623 - cores/clock: juse use 1e9/freq instead of period_ns <Florent Kermarrec> * a881817f - cores/clock/s6pll: add phase support <Florent Kermarrec> * 6b7ca0cf - cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq <Florent Kermarrec> * 1884649d - litex_term: make sure to unconfigure console when board is unplugged <Florent Kermarrec> * e052d7f6 - soc/integration/builder: -x <Florent Kermarrec> * 236070fd - cores: -x on spi.py <Florent Kermarrec> * a9fe2788 - wishbone/SRAM: make read_only emited verilog code compatible with all tools <Florent Kermarrec> * ce5c5859 - soc/cores/uart: add FT245 FIFO mode support (sync & async) <Florent Kermarrec> * a496760c - build/altera/quartus: use .bat on win32/cygwin <Florent Kermarrec> * 7e0ea070 - build/xilinx/vivado: change severity of Common 17-55 critical warning to warning <Florent Kermarrec> * 92d93ad2 - cores/pwm: remove default CSR reset values. <Florent Kermarrec> * 25ca0a8b - soc: generate git header and show migen/litex git sha1 in bios <Florent Kermarrec> * ae00482d - Merge pull request #223 from sergachev/master <enjoy-digital> * fdb119cb - support vivado incremental implementation <Ilia Sergachev> * litex-renode changed from b3fdb9b to 742360f * 742360f - Merge pull request #15 from antmicro/zephyr_dts <Tim Ansell> |\ | * c9b9651 - Add script generating DTS overlay for Zephyr <Mateusz Holenko> * | b0ebee5 - Merge pull request #14 from antmicro/memory_regions_verification <Mateusz Hołenko> |/ * ad52a03 - Verify memory sub-regions <Mateusz Holenko> * 2cb6886 - Rework handling address/size values in `Configuration` <Mateusz Holenko> * 462df23 - Simplify flash memory generation <Mateusz Holenko> * 3a1f7c8 - Generate memory regions size in hex <Mateusz Holenko> * f010339 - Print peripheral address in hex <Mateusz Holenko> * 0742996 - Fix a typo <Mateusz Holenko> * migen changed from 0.6.dev-289-g5585912 to 0.6.dev-306-g41922fd * 41922fd - sayma_amc2: amc_fpga_sysref* <Sebastien Bourdeauducq> * 3714470 - sayma_amc: fix dac_sync pin locations <Sebastien Bourdeauducq> * 4a6ef29 - sayma_amc2: DAC JESD links have been swapped <Sebastien Bourdeauducq> * 3012df6 - sayma_amc2: sma_io -> mcx_io <Sebastien Bourdeauducq> * ecf8412 - sayma2: remove serwb <Sebastien Bourdeauducq> * fc31a9e - sayma_rtm2: add HMC workaround signals <Sebastien Bourdeauducq> * 21b2fbd - sayma_rtm2: fix swapped scl/sda <Sebastien Bourdeauducq> * 0114468 - sayma_rtm2: cross UART <Sebastien Bourdeauducq> * 5a28590 - sayma_rtm2: clk50 is DNP, use GTP clock instead <Sebastien Bourdeauducq> * ef7dab2 - sayma_rtm2: always xc7a50t <Sebastien Bourdeauducq> * 63a5f55 - sayma_rtm2: add filtered_clk_sel signal <Sebastien Bourdeauducq> * 9211304 - sayma_amc2: add filtered_clk_sel signal <Sebastien Bourdeauducq> * 9e59e41 - sayma_amc2: fix typo in previous commit <Sebastien Bourdeauducq> * 58d9c82 - sayma_amc2: fix ddram_32 assignments <Sebastien Bourdeauducq> * 57a7311 - Added support for the Xilinx AC701 FPGA development board <Tobias Rosenkranz> * f4fcd10 - fix previous commit <Sebastien Bourdeauducq> * 34f24f3 - zedboard: use Vivado toolchain <Sebastien Bourdeauducq> Full submodule status -- 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (remotes/origin/HEAD) 01d8f819f15baf9a8cc5d96945a51e4d267ff564 flash_proxies (remotes/origin/HEAD) 401554f94c5fbfae1a4de98504c5c2994a6f714a litedram (remotes/origin/HEAD) 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 liteeth (remotes/origin/HEAD) 47e76f447f6e3d97aac2638a98f967d44db5c349 litepcie (remotes/origin/HEAD) db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (remotes/origin/HEAD) 7a9fa9d3b18362bf707dff25a78661395ef9ee7a litescope (remotes/origin/HEAD) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (remotes/origin/HEAD) 49bafa481075e0bfbaf067b63c351ec29e993894 litevideo (remotes/origin/HEAD) a54b80b9b4eaa6defca99b0749da8426535bbb62 litex (v0.1-1333-ga54b80b9) 742360f2ba4c400c6164908f03c6ca3d965f168b litex-renode (remotes/origin/HEAD) 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 migen (0.6.dev-306-g41922fd)

fx2_reset_PULLUP is set but the tri state is not configured #272

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