NXP's IMX RT1010 triggers assert on SPI Loopback test when EDMA enabled

[ubieda]

Describe the bug

Running SPI Loopback Test on IMX RT1010 EVK triggers a failed assert when eDMA is enabled (CONFIG_SPI_MCUX_LPSPI_DMA).

Git Bisect points to a5cf757 (from #61311), which indicates this could be a regression.

Running the same testsuite with CONFIG_SPI_MCUX_LPSPI_DMA=n works as expected.

This is the only NXP board I have with me so I don't know if other variants experience the same issue (e.g: mimxrt1015_evk, mimxrt1020, etc).

To Reproduce
Using Upstream Zephyr (main branch)

Build command:

west build -b mimxrt1010_evk tests/drivers/spi/spi_loopback/ && west flash -r jlink

Console output:

*** Booting Zephyr OS build v3.7.0-645-gedb71f0ba176 ***
Running TESTSUITE spi_loopback
===================================================================
START - test_spi_loopback
I: SPI test on buffers TX/RX 0x202040a0/0x20204080, frame size = 8, DMA enabled
I: SPI test slow config
I: Start complete multiple
ASSERTION FAIL [0] @ WEST_TOPDIR/zephyr/lib/libc/picolibc/libc-hooks.c:224
E: r0/a1:  0x00000004  r1/a2:  0x000000e0  r2/a3:  0x40184000
E: r3/a4:  0x00000004 r12/ip:  0x60004f91 r14/lr:  0x60004151
E:  xpsr:  0x21000011
E: Faulting instruction address (r15/pc): 0x60008d5c
E: >>> ZEPHYR FATAL ERROR 4: Kernel panic on CPU 0
E: Fault during interrupt handling

E: Current thread: 0x20208240 (idle)
E: Halting system
*** Booting Zephyr OS build v3.7.0-645-gedb71f0ba176 ***
Running TESTSUITE spi_loopback
===================================================================
START - test_spi_loopback
I: SPI test on buffers TX/RX 0x202040a0/0x20204080, frame size = 8, DMA enabled
I: SPI test slow config
I: Start complete multiple
ASSERTION FAIL [0] @ WEST_TOPDIR/zephyr/lib/libc/picolibc/libc-hooks.c:224
E: r0/a1:  0x00000004  r1/a2:  0x000000e0  r2/a3:  0x40184000
E: r3/a4:  0x00000004 r12/ip:  0x60004f91 r14/lr:  0x60004151
E:  xpsr:  0x21000011
E: Faulting instruction address (r15/pc): 0x60008d5c
E: >>> ZEPHYR FATAL ERROR 4: Kernel panic on CPU 0
E: Fault during interrupt handling

E: Current thread: 0x20208240 (idle)
E: Halting system

Expected behavior
Test should work with or without DMA enabled.

[ubieda]

CC: @dleach02 @decsny

[dleach02]

@Dat-NguyenDuy your PR is apparently the bisect source. Can you look at this?

[Dat-NguyenDuy]

Hi @ubieda, thanks for reporting the issue, could you run the test with this PR: #77140 as i don't have the board in my hand